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參數(shù)資料
| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 222/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SN2005118412ZHK |
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Introduction
38
September 2005
SCPS110
Table 217. CardBus PC Card Interface Control Terminals
If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.
TERMINAL
DESCRIPTION
I/O
INPUT
OUTPUT
PU/
POWER
NAME
NO.
DESCRIPTION
I/O
TYPE
INPUT
OUTPUT
PU/
PD
POWER
RAIL
CAUDIO
B12
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system
speaker. The controller supports the binary audio mode and outputs a binary
signal from the card to SPKROUT.
I/O
PCII4
PCIO4
PU3
VCCCB
CBLOCK
H15
CardBus lock. CBLOCK is used to gain exclusive access to a target.
I/O
PCII4
PCIO4
PU3
VCCCB
CCD1
N15
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in
conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards
I
TTLI2
PU4
CCD1
CCD2
N15
B11
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in
conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards
to determine the operating voltage and card type.
I
TTLI2
PU4
CDEVSEL
F19
CardBus device select. The controller asserts CDEVSEL to claim a CardBus
cycle as the target device. As a CardBus initiator on the bus, the controller
monitors CDEVSEL until a target responds. If no target responds before timeout
occurs, then the controller terminates the cycle with an initiator abort.
I/O
PCII4
PCIO4
PU3
VCCCB
CFRAME
E19
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle.
CFRAME is asserted to indicate that a bus transaction is beginning, and data
transfers continue while this signal is asserted. When CFRAME is deasserted,
the CardBus bus transaction is in the final data phase.
I/O
PCII7
PCIO7
VCCCB
CGNT
G17
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card
access to the CardBus bus after the current data transaction has been
completed.
I/O
PCII7
PCIO7
VCCCB
CINT
E12
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request
interrupt servicing from the host.
I/O
PCII4
PCIO4
PU3
VCCCB
CIRDY
F17
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to
complete the current data phase of the transaction. A data phase is completed on
a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY
and CTRDY are both sampled asserted, wait states are inserted.
I/O
PCII4
PCIO4
PU3
VCCCB
CPERR
G19
CardBus parity error. CPERR reports parity errors during CardBus transactions,
except during special cycles. It is driven low by a target two clocks following the
data cycle during which a parity error is detected.
I/O
PCII4
PCIO4
PU3
VCCCB
CREQ
C14
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card
desires use of the CardBus bus as an initiator.
I/O
PCII4
PCIO4
PU3
VCCCB
CSERR
C12
CardBus system error. CSERR reports address parity errors and other system
errors that could lead to catastrophic results. CSERR is driven by the card
synchronous to CCLK, but deasserted by a weak pullup; deassertion may take
several CCLK periods. The controller can report CSERR to the system by
assertion of SERR on the PCI interface.
I/O
PCII4
PCIO4
PU3
VCCCB
CSTOP
G18
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to
stop the current CardBus transaction. CSTOP is used for target disconnects, and
is commonly asserted by target devices that do not support burst data transfers.
I/O
PCII4
PCIO4
PU3
VCCCB
CSTSCHG
A12
CardBus status change. CSTSCHG alerts the system to a change in the card
status, and is used as a wake-up mechanism.
I
PCII6
SW1
VCCCB
CTRDY
G15
CardBus target ready. CTRDY indicates the ability of the CardBus target to
complete the current data phase of the transaction. A data phase is completed on
a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this
time, wait states are inserted.
I/O
PCII1
PCIO1
PU5
VCCCB
CVS1
CVS2
A13
B16
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are
used in conjunction with CCD1 and CCD2 to identify card insertion and
interrogate cards to determine the operating voltage and card type.
I/O
TTLI2
TTLO1
PU4
VCCCB
These terminals are reserved for the PCI7402 and PCI8402 controllers.
Table 218. Reserved Terminals
TERMINAL
DESCRIPTION
PIN STRAPPING
NAME
NUMBER
DESCRIPTION
PIN STRAPPING
RSVD
B10, H17, M19
Reserved (CardBus reserved)
Float
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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