
OHCI Registers
175
September 2005
SCPS110
8.29 Initial Channels Available Low Register
The initial channels available low register value is loaded into the corresponding bus management CSR
register on a system (hardware) or software reset. See Table 821 for a complete description of the register
contents.
OHCI register offset:
B8h
Register type:
Read/Write
Default value:
FFFF FFFFh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
1
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
1
Table 821. Initial Channels Available Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
310
InitChanAvailLo
RW
This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR
register upon a GRST, PRST, or a 1394 bus reset.
8.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval. See Table 822 for a complete description of the
register contents.
OHCI register offset:
DCh
Register type:
Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 822. Fairness Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
318
RSVD
R
Reserved. Bits 318 return 00 0000h when read.
70
pri_req
RW
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY layer during a fairness interval. The default
value for this field is 00h.