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參數(shù)資料
| 型號： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁數(shù)： | 219/271頁 |
| 文件大?。?/td> | 3240K |
| 代理商： | SN2005118412ZHK |
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Introduction
35
September 2005
SCPS110
Table 214. 16-Bit PC Card Interface Control Terminals
External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC
Card interface control terminal is unused, then the terminal may be left floating. For input, output, pullup, and
pulldown information refer to information by terminal number in Table 215, Table 216, and Table 217.
TERMINAL
DESCRIPTION
I/O
POWER
NAME
NO.
DESCRIPTION
I/O
TYPE
POWER
RAIL
BVD1
(STSCHG/RI)
A12
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used
with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are
high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced.
When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for
this signal.
Status change. STSCHG alerts the system to a change in the READY, write protect, or battery voltage dead
condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
I
VCCCB
BVD2
(SPKR)
B12
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used
with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are
high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and must be replaced.
When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change Interrupt Configuration Register, for enable bits. See Section 5.5,
ExCA Card Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the status bits for
this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and socket have been
configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the controller and
are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that
supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation.
I
VCCCB
CD1
CD2
N15
B11
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC
Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see Section 5.2, ExCA Interface
Status Register.
I
CE1
CE2
L17
K18
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables
even-numbered address bytes, and CE2 enables odd-numbered address bytes.
O
VCCCB
INPACK
C14
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current
address.
DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card
that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a
DMA operation.
I
VCCCB
IORD
J18
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during host I/O read
cycles.
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports
DMA. The controller asserts IORD during DMA transfers from the PC Card to host memory.
O
VCCCB
IOWR
J17
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards during host I/O write
cycles.
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports
DMA. The controller asserts IOWR during transfers from host memory to the PC Card.
O
VCCCB
These terminals are reserved for the PCI7402 and PCI8402 controllers.
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