
SD Host Controller Programming Model
220
September 2005
SCPS110
12.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the SD host controller PCI header type and no
built-in self-test. See Table 126 for a complete description of the register contents.
Function 3 register offset: 0Eh
Register type:
Read-only
Default value:
0080h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
Table 126. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
158
BIST
R
Built-in self-test. The SD host controller does not include a BIST; therefore, this field returns 00h when
read.
70
HEADER_TYPE
R
PCI header type. The SD host controller includes the standard PCI header. Bit 7 indicates if the SD host
is a multifunction device.
12.8 SD Host Base Address Register
The SD host base address register specifies the base address of the memory-mapped interface registers for
each standard SD host socket. The size of the base address register (BAR) is 256 bytes. See Table 127 for
a complete description of the register contents.
Function 3 register offset: 10h
Register type:
Read/Write, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 127. SD Host Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
318
BAR
RW
Base address. This field specifies the upper 24 bits of the 32-bit starting base address. The size of
the base address is 256 bytes.
74
RSVD
R
Reserved. Bits 74 return 0h when read.
3
PREFETCHABLE
R
Prefetchable indicator. This bit is hardwired to 0b to indicate that the memory space is not
prefetchable.
21
TYPE
R
This field is hardwired to 00b to indicate that the base address is located in 32-bit address space.
0
MEM_INDICATOR
R
Memory space indicator. Bit 0 is hardwired to 0b to indicate that the base address maps into memory
space.