
Principles of Operation
57
September 2005
SCPS110
Table 39. EEPROM Loading Map (Continued)
SERIAL ROM
OFFSET
BYTE DESCRIPTION
28h
PCI 2Dh, subsystem vendor ID, byte 1
29h
PCI 2Eh, subsystem ID, byte 0
2Ah
PCI 2Fh, subsystem ID, byte 1
2Bh
PCI F4h, Link_Enh, byte 0, bits 7, 2, 1
OHCI 50h, host controller control, bit 23
[7]
Link_Enh.
enab_unfair
[6]
HCControl.Program Phy Enable
[5:3]
RSVD
[2]
Link_Enh, bit 2
[1]
Link_Enh.
enab_accel
[0]
RSVD
2Ch
Mini-ROM address, this byte indicates the MINI ROM offset into the EEPROM
00h = No MINI ROM
Other Values = MINI ROM offset
2Dh
OHCI 24h, GUIDHi, byte 0
2Eh
OHCI 25h, GUIDHi, byte 1
2Fh
OHCI 26h, GUIDHi, byte 2
30h
OHCI 27h, GUIDHi, byte 3
31h
OHCI 28h, GUIDLo, byte 0
32h
OHCI 29h, GUIDLo, byte 1
33h
OHCI 2Ah, GUIDLo, byte 2
34h
OHCI 2Bh, GUIDLo, byte 3
35h
Checksum (Reserved—no bit loaded)
36h
PCI F5h, Link_Enh, byte 1, bits 7, 6, 5, 4
37h
PCI F0h, PCI miscellaneous, byte 0, bits 7, 5, 4, 2, 1, 0
38h
PCI F1h, PCI miscellaneous, byte 1, bits 70
39h
Reserved
3Ah
Reserved (CardBus CIS pointer)
3Bh
Reserved
3Ch
PCI ECh, PCI PHY control, bits 7, 3, 1
3Dh
Flash media core function indicator (02h)
3Eh
Number of bytes (05h)
3Fh
PCI 2Ch, subsystem vendor ID, byte 0
40h
PCI 2Dh, subsystem vendor ID, byte 1
41h
PCI 2Eh, subsystem ID, byte 0
42h
PCI 2Fh, subsystem ID, byte 1
43h
PCI 4Ch, general control, bits 74, 20
44h
SD host controller function indicator (03h)
45h
Number of bytes (0Bh)
46h
PCI 2Ch, subsystem vendor ID, byte 0
47h
PCI 2Dh, subsystem vendor ID, byte 1
48h
PCI 2Eh, subsystem ID, byte 0
49h
PCI 2Fh, subsystem ID, byte 1
4Ah
PCI 88h, general control bits 73, 1, 0
4Bh
PCI 94h, slot 0 3.3 V maximum current
4Ch
Reserved (PCI 98h, slot 1 3.3 V maximum current)
4Dh
Reserved (PCI 9Ch, slot 2 3.3 V maximum current)