
12. DMAC
Table 12.2
DMiSL Register (i = 0 to 3) Function
NOTES:
1.
The falling edge or both edges of input signal to the INTi pin cause to generate a DMA request. They do not affect the INT interrupt
(bits POL and LVS in the INTiIC register, the IFSR register) and vice versa.
2.
To switch between the UARTj receive and ACK (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on the UiSMR2
register. To use the ACK interrupt, set the IICM bit to 1 (I2C mode) and the IICM2 bit to 0 (NACK/ACK interrupt).
3.
The same setting is used to generate a CAN10 request and a UART5 receive interrupt.
4.
The same setting is used to generate a CAN20 request.
5.
The same setting is used to generate a CAN00 request, an INT6 interrupt, and a UART6 receive interrupt.
6.
The same setting is used to generate a CAN11 request, and a UART5 transmit interrupt.
7.
The same setting is used to generate a CAN21 request.
8.
The same setting is used to generate a CAN01 request, an INT7 interrupt, and a UART6 transmit interrupt.
9.
The same setting is used to generate a CAN02 request, and an INT8 interrupt.
10. The same setting is used to generate a CAN22 request.
11. The same setting is used to generate a CAN12 request.
Setting Value
DMA Request Source
b4
b3
b2
b1
b0
DMA0
DMA1
DMA2
DMA3
0000
0
Software trigger
0000
1Falling edge of INT0
Falling edge of INT1
Falling edge of INT2
Falling edge of INT3
(Note 1)
0001
0Both edges of INT0
Both edges of INT1
Both edges of INT2
Both edges of INT3
(Note 1)
0001
1
Timer A0 interrupt request
0010
0
Timer A1 interrupt request
0010
1
Timer A2 interrupt request
0011
0
Timer A3 interrupt request
0011
1
Timer A4 interrupt request
0100
0
Timer B0 interrupt request
0100
1
Timer B1 interrupt request
0101
0
Timer B2 interrupt request
0101
1
Timer B3 interrupt request
0110
0
Timer B4 interrupt request
0110
1
Timer B5 interrupt request
0111
0
UART0 transmit interrupt request
0111
1
UART0 receive or ACK interrupt request
(2)1000
0
UART1 transmit interrupt request
1000
1
UART1 receive or ACK interrupt request
(2)1001
0
UART2 transmit interrupt request
1001
1
UART2 receive or ACK interrupt request
(2)1010
0
UART3 transmit interrupt request
1010
1
UART3 receive or ACK interrupt request
(2)1011
0
UART4 transmit interrupt request
1011
1
UART4 receive or ACK interrupt request
(2)1100
0
A/D0 interrupt request
A/D0 interrupt request
1100
1Intelligent I/O interrupt 0
Intelligent I/O interrupt 7
request
Intelligent I/O interrupt 2
Intelligent I/O interrupt 9
1101
0Intelligent I/O interrupt 1
Intelligent I/O interrupt 8
request
Intelligent I/O interrupt 3
Intelligent I/O interrupt 10
1101
1Intelligent I/O interrupt 2
Intelligent I/O interrupt 9
Intelligent I/O interrupt 4
request
Intelligent I/O interrupt 11
1110
0Intelligent I/O interrupt 3
Intelligent I/O interrupt 10
Intelligent I/O interrupt 5
Intelligent I/O interrupt 0
1110
1Intelligent I/O interrupt 4
request
Intelligent I/O interrupt 11
Intelligent I/O interrupt 6
Intelligent I/O interrupt 1
1111
0Intelligent I/O interrupt 5
Intelligent I/O interrupt 0
Intelligent I/O interrupt 7
request
Intelligent I/O interrupt 2
1111
1Intelligent I/O interrupt 6
Intelligent I/O interrupt 1
Intelligent I/O interrupt 8
request
Intelligent I/O interrupt 3