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16.2.2
Clock Asynchronous Serial Interface (UART) Mode
In UART mode, a given baud rate and transfer data format can be selected to transmit and receive data.
Table 16.47lists specifications of UART mode.
Table 16.47
UART Mode Specifications
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an overrun error occurs, the content of the UiRB register is undefined. The U5RR bit in the IIO0IR register
and the U6RR bit in the IIO9IR register remain unchanged as 0 (interrupt not requested).
Item
Specification
Transfer data format
Transfer data length: selectable among 7 bits, 8 bits, or 9 bits long
Start bit: 1 bit long
Parity bit: selectable among odd, even, or none
Stop bit: selectable among 1 bit or 2 bits long
Baud rate
When the CKDIR bit in the UiMR register (i = 5, 6) is set to 0 (internal clock):
fj / (16 (m + 1))
fj = f1, f8, f2
n(1) m: setting value of the UiBRG register, 00h to FFh
When the CKDIR bit is set to 1 (external clock):
fEXT / (16 (m + 1))
fEXT: external clock rate
Transmit/receive control
Selectable among CTS function, RTS function or CTS/RTS function disabled
Transmit start condition
To start transmit operation, the following must be met:
Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
The TI bit in the UiC1 register is 0 (data in the UiTB register)
Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
Receive start condition
To start receive operation, the following must be met:
Set the RE bit in the UiC1 register to 1 (receive operation enabled)
The start bit is detected
Interrupt request generation timing While transmitting, one of the following conditions can be selected:
The UiIRS bit in the U56CON register is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit register
(transmit operation started)
The UiIRS bit is set to 1 (transmit operation completed):
when data transmit operation from the UARTi transmit register is completed
While receiving,
When data is transferred from the UARTi receive register to the UiRB register
(receive operation completed)
Error detection
Overrun error occurs when the bit preceding the final stop bit of the next data
(the first stop bit when selecting 2 stop bits) is received before reading the UiRB
register
Framing error
Framing error occurs when the number of the stop bits set using the STPS bit in
the UiMR register is not detected
Parity error
Parity error occurs when parity is enabled and the received data does not have
the correct even or odd parity set with the PRY bit in the UiMR register.
Error sum flag
Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs
Selectable function
LSB first or MSB first
Data is transmitted or received from either bit 0 or bit 7