
25. Flash Memory
25.1.1
Boot Mode
The MCU enters boot mode when a hardware reset is performed while a high-level (“H”) signal is applied to
the CNVSS pin, a low-level (“L”) signal is applied to the P5_5 (EPM) pin, and an “H” is applied to the P5_0
(CE) pin. And then, a program in the boot ROM area is executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to either a boot ROM area or a user ROM
area.
The boot ROM area stores the rewrite control program for the standard serial I/O mode in the factory default
configuration.
The boot ROM area can be rewritten in parallel I/O mode. If a given rewrite control program is written in the
boot ROM area, the flash memory can be rewritten along the implemented system.
25.2
Functions to Prevent Access to Flash Memory
Parallel I/O mode has a ROM code protect function, and standard I/O mode has an ID code check function to
prevent the flash memory from being read or rewritten.
25.2.1
ROM Code Protect Function
The ROM code protect function disables reading or rewriting the contents of the flash memory in parallel I/O
mode. To use ROM code protect function, set the ROMCP1 bits in the ROMCP address.
The ROMCP address is located in a user ROM area.
Figure 25.2 shows the ROMCP address.
25.2.2
ID Code Check Function
The ID code check function is used in standard serial I/O mode. The ID code sent from the serial programmer
and the ID code written in the flash memory are checked to see if they match. If these ID codes do not match,
the commands sent from the serial programmer are not acknowledged. However, if the four bytes of the reset
vector are set to FFFFFFFFh(1), the ID code is not checked and all commands can be acknowledged.
The ID code is 7-byte data stored consecutively, beginning with the first byte, into addresses 0FFFFDFh,
0FFFFE3h, 0FFFFEBh, 0FFFFEFh, 0FFFFF3h, 0FFFFF7h, and 0FFFFFBh. Write the program in which the ID
code is set in these addresses to the flash memory.
NOTE:
1. FFFFFFFFh is set in the factory default configuration.