
22. 16-Slot CAN Module
Figure 22.10
Bit Timing Diagram
22.1.8
CANi Time Stamp Register (CiTSR Register) (i = 0, 1)
Figure 22.11
C0TSR and C1TSR Registers
The CiTSR register is a 16-bit counter. Bits TSPRE1 and TSPRE0 in the CiCTLR0 register determine the CAN
bus bit clock divided by 1, 2, 3, or 4 as the count source.
When a transmit or receive operation is completed, the value of the CiTSR register is automatically stored into
the message slot.
In loopback mode, the value of the CiTSR register is stored into the data frame receive message slot or remote
frame receive message slot when a receive operation is completed, if the corresponding message slot is
available to store the message. The value of the CiTSR register is not stored when a transmit operation is
completed in loopback mode.
The CiTSR register starts a counter increment when bits RESET1 and RESET0 in the CiCTLR0 register are set
to 0 (CAN module is out of reset).
The CiTSR register becomes 0000h when one of the following events occur:
at the next count timing after the CiTSR register becomes FFFFh,
when both bits RESET1 and RESET0 are set to 1 (CAN module is reset) by program,
when the TSRESET bit in the CiCTLR0 register is set to 1 (CiTSR register reset) by program.
1
CAN bit time
Setting range of each segment
CAN bit time = 8Tq to 25Tq
SS = 1Tq
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
SJW = 1Tq to 4Tq
SS
CAN Bit Time
PTS
PBS1
PBS2
SJW
Sampling point
SJW
Condition of PBS1 and PBS2:
PBS1 ≥ PBS2 ≥ SJW
b15
b7
Symbol
C0TSR
C1TSR
Address
0209h - 0208h
0289h - 0288h
After Reset(1)
0000h
b0
Function
RW
CANi Time Stamp Register (i = 0, 1)
RO
Value of time stamp
NOTE:
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
to the CAN module.
b8
CAN bus bit clock =