![](http://datasheet.mmic.net.cn/30000/M30956FKTGP_datasheet_2359453/M30956FKTGP_232.png)
Figure 16.11
Transmit and Receive Operations in Clock Synchronous Serial Interface Mode
Internal clock
(1) Transmit timing (when internal clock is selected)
Meet the following conditions while an "H" signal is applied to
the CLKi pin before data is received:
- TE bit in UiC1 register = 1 (transmit enable)
- RE bit in UiC1 register = 1 (receive enable)
- Write dummy data to the UiTB register
1
0
fEXT
: External clock frequency
The above applies under the following conditions:
- CKDIR bit in UiMR register = 1 (external clock selected)
- CRD bit in UiC0 register = 1 (CTS function disabled)
- CKPOL bit in UiC0 register = 0 (received data is input at the rising edge of
the serial clock)
1
0
"H"
"L"
1
0
1
0
(2) Receive timing (when external clock is selected)
TE bit in
UiC1 register
TI bit in
UiC1 register
Input to CTSi
Output
from CLKi
Output
from TXDi
TXEPT bit in
UiC0 register
IR bit in
SiTIC register
i = 0 to 4
The above applies under the following conditions:
- CKDIR bit in UiMR register = 0 (internal clock)
- CRD bit in UiC0 register = 0 (CTS function enabled), and
CRS bit in UiC0 register = 0 (CTS function selected)
- CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge of
the serial clock)
- UiIRS bit in UiC1 register = 0 (interrupt request generated when no data
in the UiTB register)
Set to 0 by an interrupt request acknowledgement or by program
Communication stops because TE bit = 0
Communication stops because CTSi = "H"
TCLK
1
0
1
0
1
0
1
0
"H"
"L"
TC
Data is set in the UiTB register
Data is transferred from the UiTB register to the UARTi transmit register
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TC = TCLK = 2(m + 1) / fj
fj: Count source frequency set in the UiBRG register (f1, f8, f2n(1))
m: Setting value of the UiBRG register
NOTE:
1. Bits CNT3 to CNT0 in the TCSPR register select either no
division (n = 0) or divide-by-2n (n = 1 to 15).
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D7
1/fEXT
Dummy data is set in
the UiTB register
Data is transferred from the UiTB register to
the UARTi transmit register
Set to 0 by an interrupt request acknowledgement or by program
Read by the UiRB register
Data is transferred from the UARTi
transmit register to the UiRB register
RE bit in
UiC1 register
TE bit in
UiC1 register
TI bit in
UiC1 register
Output
from RTSi
Input to CLKi
Input to RXDi
RI bit in
UiC1 register
IR bit in
SiRIC register
D6
OER bit in
UiRB register
"L" is output by reading the UiRB register
Received data is captured
1
0
1
0