![](http://datasheet.mmic.net.cn/30000/M30956FKTGP_datasheet_2359453/M30956FKTGP_273.png)
Figure 16.30
SIM Interface Operation
Serial clock
Signal line level(2)
Parity error signal
returned from
receiving end
TE bit
in UiC1 register
TXEPT bit in
UiC0 register
Signal line level(3)
Transmit waveform
from transmitting end
TXDi
The above applies under the following conditions:
- PRYE bit in UiMR register = 1 (parity enabled)
- STPS bit in UiMR register = 0 (1 stop bit)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
D7
P
ST
D0
D1
D2
D3
D4
D5
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
D7
P
ST
D0
D1
D2
D3
D4
D5
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
TE bit
in UiC1 register
TXDi
IR bit in
SiTIC register
IR bit in
SiRIC register
NOTES:
1. Transmit operation is started when UiBRG overflows after a value is set in the UiTB register in the indicated timing.
2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity
error signal from the receiving end, is generated.
3. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the transmitting end and
parity error signal from the TXDi pin, is generated.
4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
Read the UiRB register
Set to 0 by an interrupt request acknowledgement or by program
TC = 16 ( n + 1) / fj
fj: Count source frequency of the UiBRG register (f1, f8, f2n(4))
n: Setting value of the UiBRG register
i = 0 to 4
The above applies under the following conditions:
- PRYE bit in UiMR register = 1 (parity enabled)
- STPS bit in UMR register = 0 (1 stop bit)
- UiIRS bit in UiC1 register = 1 (transmit operation is completed)
Set to 0 by an interrupt request acknowledgement or by program
TC = 16 ( n + 1) / fj
fj: Count source frequency of the UiBRG register (f1, f8, f2n(4))
n: Setting value of the UiBRG register
The SIM card outputs "L"
because a parity error occurs
Detect the level in
interrupt routine
0
1
TC
Start
bit
Parity
bit
Stop
bit
(Note 1)
TC
TXDi outputs "L"
because a parity error occurs
(1) When transmitting
(2) When receiveing
0
1
0
1
0
1
Data is transferred from the UiTB register
to the UARi transmit register
Data is set in the UiTB register
SP
Detect the level in
interrupt routine
Serial clock
RE bit
in UiC1 register
0
1
RE bit
in UiC1 register
0
1
0
1
Start
bit
Parity
bit
Stop
bit
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P