
After UARTi (i = 0 to 4) operating mode is selected and the pin function is set with function select register, the
TXDi pin outputs a high-level (“H”) signal until a transfer starts (the TXDi pin is in a high-impedance state
when N-channel open drain output is selected).
receive operation in UART mode.
Table 16.8
Register Settings in UART Mode
i = 0 to 4
NOTE:
1. Use bits 6 to 0 when transfer data is 7 bits long, bits 7 to 0 when 8 bits long, and bits 8 to 0 when 9 bits long.
Register
Bit
Setting Value
UiMR
SMD2 to SMD0
Set to 100b when transfer data length is 7 bits long
Set to 101b when transfer data length is 8 bits long
Set to 110b when transfer data length is 9 bits long
CKDIR
Select the internal clock or external clock
STPS
Select stop bit length
PRY, PRYE
Select parity enabled or disabled, and odd or even
IOPOL
Select TXD and RXD I/O polarity
UiSMR
7 to 0
Set to 00h
UiSMR2
7 to 0
Set to 00h
UiSMR3
7 to 0
Set to 00h
UiSMR4
7 to 0
Set to 00h
UiC0
CLK1, CLK0
Select the count source of the UiBRG register
CRS
Select the CTS function
TXEPT
Transfer register empty flag
CRD
Enable or disable the CTS function
NCH
Select output format of the TXDi pin
CKPOL
Set to 0
UFORM
Select the LSB first or MSB first when a transfer data length is 8 bits long.
Set to 0 when transfer data length is 7 bits or 9 bits long
UiBRG
7 to 0
Set baud rate
UiC1
TE
Set to 1 to enable transmit operation
TI
Transfer buffer empty flag
RE
Set to 1 to enable receive operation
RI
Receive operation complete flag
UiIRS
Select a UARTi transmit interrupt source
UiLCH
Select data logic inverted or data logic not inverted when a transfer data
length is 7bits or 8 bits long.
Set to 0 when transfer data length is 9 bits
long.
UiERE
Set to either 0 or 1
UiTB
8 to 0
UiRB
8 to 0
Receive data can be read
(1)OER, FER, PER, SUM
Error flags