
23. 32-Slot CAN Module
23.1
CAN-Associated Registers
below before accessing the CAN-associated registers:
(1) set the CM21 bit in the CM2 register to 0 (use main clock or PLL clock as the CPU clock)
(2) when the PM35 bit in the PM3 register is set to 1 (fPFC divided by 2), set bits MCD4 to MCD0 to 00010b
(divide-by-2 mode)
when the PM35 bit in the PM3 register is set to 0 (fPFC not divided), set bits MCD4 to MCD0 to 10010b
(no division mode)
(3) set the PM13 bit in the PM1 register to 1 (2 wait states)
23.1.1
CAN2 Control Register 0 (C2CTLR0 Register)
Figure 23.3
C2CTLR0 Register
Symbol
Address
After Reset(1)
RW
CAN2 Control Register 0
C2CTLR0
0501h - 0500h
XXXX 0000 XX01 0X01b
Function
Bit Symbol
Bit Name
RW
RW
CAN reset bit 0(2)
0: CAN module is out of reset
1: CAN module is reset
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
BasicCAN mode select bit
0: BasicCAN mode function disabled
1: BasicCAN mode function enabled
RW
Reserved bit
b7
b8
b15
b0
RW
CAN reset bit 1(2)
Set to 0
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
Loop back mode select bit
0: Loop back function disabled
1: Loop back function enabled
0: CAN module is out of reset
1: CAN module is reset
Time stamp prescaler
select bits
RW
b9 b8
0 0: CAN bus bit clock
0 1: CAN bus bit clock divided by 2 selected
1 0: CAN bus bit clock divided by 3 selected
1 1: CAN bus bit clock divided by 4 selected
RW
Error counter reset bit
RW
Time stamp counter reset bit
0: Nothing occurs
1: Registers C2TEC and CiREC become 00h,
then this bit is automatically set back to 0
0: Nothing occurs
1: The C2TSR register becomes 0000h, then
this bit is automatically set back to 0
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
RESET0
LOOPBACK
(b2)
RESET1
(b7-b6)
(b5)
BASICCAN
TSPRE0
TSPRE1
TSRESET
ECRESET
(b15-b12)
0
NOTES:
1. The value is obtained by setting the SLEEP bit in the C2SLPR register to 1 (sleep mode exited) after reset and supplying the clock
to the CAN module.
2. Set bits RESET1 and RESET0 to the same value simultaneously.
RW