
16.2.1
Clock Synchronous Serial Interface Mode
In clock synchronous serial interface mode, data is transmitted and received using the serial clock.
Table 16.42 lists specifications of clock synchronous serial interface mode.
Table 16.43 lists register settings.
Tables
16.44 to
16.46 list pin settings. After UARTi (i = 5 and 6) operating mode is selected and the pin function is
set with function select register, the TXDi pin outputs a high-level (“H”) signal until a transfer starts.
Figure 16.40shows transmit and receive timings in clock synchronous serial interface mode.
Table 16.42
Clock Synchronous Serial Interface Mode Specifications
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
UiC0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the
serial clock), and that an “L” signal is applied when the CKPOL bit is set to 1 (transmit data output at the rising
edge and receive data input at the falling edge of the serial clock).
3. If an overrun error occurs, the content of the UiRB register is undefined. The U5RR bit in the IIO0IR register
and the U6RR bit in the IIO9IR register remain unchanged as 0 (interrupt not requested).
Item
Specification
Transfer data format
Transfer data length: 8 bits long
Serial clock
Internal clock or external clock can be selected with the CKDIR bit in the UiMR
register (i = 5 and 6).
Baud rate
When the CKDIR bit is set to 0 (internal clock):
fj / (2 (m + 1))
fj = f1, f8, f2n
(1) m: setting value of the UiBRG register, 00h to FFh
When the CKDIR bit is set to 1 (external clock): external clock rate
Transmit/receive control
Selectable among the CTS function, RTS function, or CTS/RTS function disabled
Transmit start condition
To start transmit operation, the following must be met
(2): Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
The TI bit in the UiC1 register is 0 (data in the UiTB register)
Apply a low-level (“L”) signal to the CTSi pin when the CTS function is selected
Receive start condition
To start receive operation, the following must be
met(2):
Set the RE bit in the UiC1 register to 1 (receive operation enabled)
Set the TE bit to 1 (transmit operation enabled)
The TI bit is 0 (data in the UiTB register)
Interrupt request generation timing While transmitting, one of the following conditions can be selected:
The UiIRS bit in the U56CON register is set to 0 (no data in the transmit buffer):
when data is transferred from the UiTB register to the UARTi transmit register
(transmit operation started)
The UiIRS bit is set to 1 (transmit operation is completed):
when data transmit operation from the UARTi transmit register is completed
While receiving:
When data is transferred from the UARTi receive register to the UiRB register
(receive operation is completed)
Error detection
Overrun error occurs when the seventh bit of the next data is received before
reading the UiRB register
Selectable function
CLK polarity
One of the following can be selected for transferring data input/output timing;
Transmit data output at the falling edge and receive data input at the rising edge
of the serial clock, or transmit data output at the rising edge and receive data
input at the falling edge of the serial clock.
LSB first or MSB first
Data is transmitted and received from either bit 0 or bit 7