
Figure 16.8
U0C1 to U4C1 Registers, U0BRG to U4BRG Registers
b7 b6 b5 b4
b1
b2
b3
Symbol
U0C1 to U2C1
U3C1, U4C1
Address
036Dh, 02EDh, 033Dh
032Dh, 02FDh
After Reset
0000 0010b
b0
Function
Bit Symbol
Bit Name
RW
RE
TI
TE
(b5)
UiLCH
0: No Data in the UiRB register
1: Data in the UiRB register
Receive complete flag
Data logic select bit(1)
Transmit enable bit
UilRS
RI
0: No data in the UiTB register (TI = 1)
1: Transmit operation is completed (TXEPT = 1)
0: Not inverted
1: Inverted
UARTi transmit interrupt source
select bit
Set to 0
Reserved bit
Clock-divided synchronous
stop bit/
Error signal output enable bit(2)
Clock-divided synchronous stop bit
(special mode 3)
0: Synchronization stopped
1: Synchronization started
Error signal output enable bit (special mode 5)
0: Not output
1: Output
SCLKSTPB/
UiERE
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
RW
RO
RW
RO
RW
Receive enable bit
0: Receive operation disabled
1: Receive operation enabled
0: Transmit operation disabled
1: Transmit operation enabled
NOTES:
1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous serial interface
mode), 100b (UART mode, 7-bit transfer data length), or 101b (UART mode, 8-bit transfer data length). Set the UiLCH bit to 0
when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit transfer data length).
2. Set bits SMD2 to SMD0 before setting the SCLKSTPB/UiERE bit.
Transmit buffer empty flag
0: Data in the UiTB register
1: No data in the UiTB register
b7
Symbol
U0BRG to U2BRG
U3BRG, U4BRG
Address
0369h, 02E9h, 0339h
0329h, 02F9h
After Reset
Undefined
b0
Function
RW
If the setting value is n,
the UiBRG register divides a count source by n+1
00h to FFh
UARTi Baud Rate Register(1, 2, 3) (i = 0 to 4)
WO
Setting Range
NOTES:
1. Use the MOV instruction to set the UiBRG register.
2. Set the UiBRG register while no data transfer occurs.
3. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
0