
11. Watchdog Timer
11. Watchdog Timer
The watchdog timer enables to detect the program running improperly. The watchdog timer contains a 15-bit counter,
which is decremented by the clock that is the BCLK divided by the prescaler. The CM06 bit in the CM0 register
determines whether a watchdog timer interrupt request is generated or a reset is performed when the watchdog timer
underflows. Once the CM06 bit is set to 1 (reset), it cannot be changed to 0 (watchdog timer interrupt) by program. The
CM06 bit is set to 0 only after reset.
When the main clock, on-chip oscillator clock, or PLL clock runs as the source of BCLK, the WDC7 bit in the WDC
register determine whether the prescaler divides the clock by 16 or by 128. When the sub clock runs as the source of
the BCLK, the prescaler divides the clock by 2 regardless of a WDC7 bit setting. Watchdog timer cycle is calculated as
follows. Marginal errors, due to the nature of prescaler, may occur in watchdog timer cycle.
When the main clock, on-chip oscillator clock, or PLL clock is selected as the source of the BCLK,
When the sub clock is selected as the source of the BCLK,
For example, if the BCLK frequency is 30MHz and the prescaler divides it by 16, a watchdog timer cycle is
approximately 17.5 ms.
The watchdog timer is initialized when writing to the WDTS register or when the watchdog timer interrupt request is
generated. The prescaler is initialized after a reset has performed. Both watchdog timer and prescaler stop out of reset.
Their count starts by writing to the WDTS register.
Set the WDTS register to shorter cycle than a watchdog timer cycle.
The watchdog timer and prescaler stop when the MCU is placed in stop mode or wait mode. They resume counting
from a value held, when the mode is exited.
Figure 11.1 shows a block diagram of the watchdog timer. Figures
11.2 and
11.3 show registers associated with the
watchdog timer.
Figure 11.1
Watchdog Timer Block Diagram
Watchdog timer cycle
=
divide-by-16 or -128 prescaler
× counter value of watchdog timer (32768)
BCLK frequency
Watchdog timer cycle
=
divide-by-2 prescaler
× counter value of watchdog timer (32768)
BCLK frequency
1/16
Prescaler
CM07=0
WDC7=0
BCLK
CM06, CM07: Bits in the CM0 register
WDC7: Bit in the WDC register
PM22: Bit in the PM2 register
CM06=0
Watchdog timer
interrupt request
PM22=0
CM07=0
WDC7=1
CM07=1
PM22=1
Set to
7FFFh
Watchdog timer
CM06=1
Reset
On-chip oscillator clock
Write to the WDTS register
Internal reset signal
1/128
1/2