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型號(hào)：	M30956FKTGP
元件分類：	微控制器/微處理器
英文描述：	FLASH, 64 MHz, MICROCONTROLLER, PQFP100
封裝：	14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)：	188/579頁(yè)
文件大?。?/td>	12750K
代理商：	M30956FKTGP

Page 243 of 551

When an output signal level from the TXDi pin (i = 0 to 4) differs from an input signal level to the RXDi pin, a

UARTi bus conflict detect interrupt request is generated.

UART0 bus conflict detect interrupts share the interrupt vector with UART3 bus conflict detect interrupts.

UART1 bus conflict detect interrupts share the interrupt vector with UART4 bus conflict detect interrupts.

To use the UART0 bus conflict detect function, set the IFSR6 bit in the ISFR register to 1 (UART0 bus conflict,

start condition detect, stop condition detect). To use the UART3 bus conflict detect function, set the IFSR6 bit

to 0 (UART3 bus conflict, start condition detect, stop condition detect).

To use the UART1 bus conflict detect function, set the IFSR7 bit in the ISFR register to 1 (UART1 bus conflict,

start condition detect, stop condition detect). To use the UART4 bus conflict detect function, set the IFSR7 bit

to 0 (UART4 bus conflict, start condition detect, stop condition detect).

When the ABSCS bit in the UiSMR register is set to 0 (rising edge of the serial clock), a level output from the

TXD pin and a level input to the RXD pin are sampled to detect mismatch between these two levels at the rising

edge of the serial clock. When the ABSCS bit is set to 1 (timer Ai underflow), these two levels are sampled

when timer Aj (j = 0 to 4) (timer A3 in UART0, timer A4 in UART1, timer A0 in UART2, timer A3 in UART3,

timer A4 in UART4) underflows. Use timer Aj in one-shot timer mode.

When the ACSE bit in the UiSMR register is set to 1 (auto cleared when bus conflict occurs) and the IR bit in

the BCNiIC register to 1 (mismatch detected), the TE bit in the UiC1 register is set to 0 (transmit operation

When the SSS bit in the UiSMR register is set to 1 (synchronized with RXDi), data is transmitted from the

TXDi pin at the falling or rising edge of the RXDi pin. Figure 16.29 shows an example of an operation in IE

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