![](http://datasheet.mmic.net.cn/30000/M30956FKTGP_datasheet_2359453/M30956FKTGP_328.png)
21. Intelligent I/O
Figure 21.4
G0TMCR0 to G0TMCR7 and G1TMCR0 to G1TMCR7 Registers
G0TPR6, G0TPR7, G1TPR6, and G1TPR7 Registers
0: Not used
1: Used
Gate function is disabled by setting the GSC
bit to 1
0: Gate function is not disabled by matching the
base timer and the GiPOk register (k = 4, 5)
1: Gate function is disabled by matching the base
timer and the GiPOk register
0: Not used
1: Used
b3 b2
0 0: No digital filter
0 1: Do not set to this value
1 0: Use digital filter (use fBTi as sampling clock)
1 1: Use digital filter (use f1 as sampling clock)
Symbol
Address
After Reset
RW
Group i Time Measurement Control Register j (i = 0, 1, j = 0 to 7)
G0TMCR0 to G0TMCR3
G0TMCR4 to G0TMCR7
G1TMCR0 to G1TMCR3
G1TMCR4 to G1TMCR7
00h
b7 b6 b5 b4
b1
b2
b3
b0
Function
Bit Symbol
Bit Name
CTS0
b1 b0
0 0: No time measurement
0 1: Rising edge
1 0: Falling edge
1 1: Both edges
CTS1
DF0
DF1
GT
GOC
RW
GSC
RW
Digital filter select bits
Gate function select bit(1)
Time measurement trigger
select bits
Gate function clear
select bit(1, 2)
Gate function clear bit(1, 2)
PR
RW
Prescaler function select bit(1)
Symbol
Address
After Reset
RW
Group i Time Measurement Prescaler Register j (i = 0, 1, j = 6, 7)
G0TPR6, G0TPR7
G1TPR6, G1TPR7
00E4h, 00E5h
0124h, 0125h
00h
b7
b0
Setting Range
Function
If the setting value is
n, the base timer value is stored into the
GiTMj register every time a trigger input is counted up to
n+1(1)
NOTE:
1. After the PR bit in the GiTMCRj register is changed from 0 (prescaler function not used) to 1 (prescaler function used), the first
prescaler cycle may be divided by
n rather than n+1. The 2nd or later prescaler cycle becomes divided by n+1.
00D8h, 00D9h, 00DAh, 00DBh
00DCh, 00DDh, 00DEh, 00DFh
0118h, 0119h, 011Ah, 011Bh
011Ch, 011Dh, 011Eh, 011Fh
00h to FFh
NOTES:
1. Gate function bits (bits GT, GOC, and GSC) and the prescaler function bit (PR bit) can be found in registers GiTMCR6 and
GiTMCR7 only. Set each bit 7 to 4 in registers GiTMCR0 to GiTMCR5 to 0.
2. Bits GOC and GSC are enabled only when the GT bit is set to 1.