
16.1.4
Special Mode 2
In special mode 2, serial communication between one or multiple masters and multiple slaves is available.
The serial bus communication is controlled using the SSi input pin (i = 0 to 4).
Table 16.22 lists specifications
Table 16.22
Special Mode 2 Specifications
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
2. If an external clock is selected, ensure that an “H” signal is applied to the CLKi pin when the CKPOL bit in the
UiC0 register is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the
serial clock), and that an “L” signal is applied when the CKPOL bit is set to 1 (transmit data output at the rising
edge and receive data input at the falling edge of the serial clock).
3. If an overrun error occurs, the content of the UiRB register is undefined. The IR bit in the SiRIC register remains
unchanged as 0 (interrupt not requested).
Item
Specification
Transfer data format
Transfer data length: 8 bits long
Baud rate
The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock):
fj / (2 (m + 1))
fj = f1, f8, f2n
(1) m: setting value of the UiBRG register, 00h to FFh
The CKDIR bit to 1 (external clock): external clock rate
Transmit/receive control
SS function
Transmit start condition
To start transmit operation, the following must be met
(2):
Set the TE bit in the UiC1 register to 1 (transmit operation enabled)
The TI bit in the UiC1 register is 0 (data in the UiTB register)
Receive start condition
To start receive operation, the following must be met
(2): Set the RE bit in the UiC1 register to 1 (receive operation enabled)
Set the TE bit to 1 (transmit operation enabled)
The TI bit is 0 (data in the UiTB register)
Interrupt request generation timing While transmitting, one of the following conditions can be selected:
The UiIRS bit in the UiC1 register is set to 0 (no data in the UiTB register):
when data is transferred from the UiTB register to the UARTi transmit register
(transmit operation started)
The UiIRS bit is set to 1 (transmit operation completed):
when a data transmit operation from UARTi transmit register is completed
While receiving,
when data is transferred from the UARTi receive register to the UiRB register
(receive operation completed)
Error detection
Overrun error occurs when the seventh bit of the next data is received before
reading the UiRB register
Mode error
Mode error occurs when an “L” signal is applied to the SSi pin in master mode
Selectable function
CLK polarity
One of the following can be selected for transmit/receive data timing:
-Transmit data at the falling edge; receive data at the rising edge
of the serial clock
-Transmit data at the rising edge; receive data at the falling edge
LSB first or MSB first
Data is transmitted or received from either bit 0 or bit 7
Serial data logic inverse
Transmit and receive data are logically inverted
TXD and RXD I/O polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted.
Clock phase
One of four combinations of serial clock polarity and phase can be selected
SSi input pin function
Output pin is placed in a high-impedance state to avoid data conflict between a
master and other masters, or a slave and other slaves.