
17. A/D Converter
Table 17.1
A/D Converter Specifications
NOTES:
1. Analog input voltage does not depend on use of the sample and hold function.
2. The
φAD frequency must be16 MHz or lower when VCC = 4.2 to 5.5 V.
Without the sample and hold function, the
φAD frequency must be 250 kHz or higher.
With the sample and hold function, the
φAD frequency must be 1 MHz or higher.
3. AVCC = VREF = VCC, AD input (AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7,
ANEX0, ANEX1)
≤ VCC.
Item
Specification
A/D conversion method
Successive approximation (with capacitance coupled amplifier)
0 V to AVCC (VCC)
Operating clock
fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8
Resolution
Selectable from 8 bits or 10 bits
Operating modes
One-shot mode
Repeat mode
Single sweep mode
Repeat sweep mode 0
Repeat sweep mode 1
Multi-port single sweep mode
Multi-port repeat sweep mode 0
34 pins
8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7), AN2 (AN2_0 to
AN2_7), AN15 (AN15_0 to AN15_7)
2 extended input pins (ANEX0 and ANEX1)
A/D conversion start condition
Software trigger
The ADST bit in the AD0CON0 register is set to “1” (A/D conversion starts)
External trigger (re-trigger is enabled)
When a falling edge is applied to the ADTRG pin after the ADST bit is set to 1
Hardware trigger (re-trigger is enabled)
Timer B2 interrupt request of the three-phase motor control timer function (after
the ICTB2 register completes counting) is generated after the ADST bit is set
to 1
Conversion rate per pin
Without sample and hold function
8-bit resolution: 49
φAD cycles, 10-bit resolution: 59 φAD cycles
With sample and hold function
8-bit resolution: 28
φAD cycles, 10-bit resolution: 33 φAD cycles