
15. Three-Phase Motor Control Timer Function
Figure 15.9
TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers
Symbol
TA1, TA2, TA4
TA11, TA21, TA41
Address
0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh
0303h - 0302h, 0305h - 0304h, 0307h - 0306h
After Reset
Undefined
Function
RW
Timer Ai, Ai-1 Register (1, 2, 3, 4, 5, 6) (i = 1, 2, 4)
WO
If the setting value is
n, the nth count source is counted after the
start trigger is generated, and the timer stops. Positive phase
changes to negative phase, and vice versa, when timers A1, A2,
and A4 stop.
NOTES:
1. Write this register in words, using the MOV instruction.
2. If the TAi or TAi1 register is set to 0000h, no counter starts and the timer Ai interrupt is not generated.
3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled) and a phase becomes active level
from inactive one, the phase changes its level after the dead time timer stops.
4. When the INV11 bit is set to 0 (three-phase mode 0), the contents of the TAi register are transferred to the reload register by a
timer Ai start trigger. When the INV11 bit is set to 1 (three-phase mode 1), the contents of the TAi1 register are transferred by
the first timer Ai start trigger, and then those of the TAi register is transferred by the next trigger. Subsequently, the contents of
registers TAi and TAi1 are transferred alternately to the reload register by each timer Ai start trigger.
5. Do not set registers TAi and TAi1 registers in the timer B2 underflow timing.
6. Set the TAi1 register in the following procedure:
(1) Write a set value to the TAi1 register.
(2) Wait for 1 cycle of the timer Ai count source.
(3) Write the same set value to the TAi1 register again.
Setting Range
0000h to FFFFh
b15
b0
b7
b8
Three-Phase Output Buffer Register i(1) (i = 0, 1)
Symbol
IDB0, IDB1
Address
030Ah, 030Bh
Bit Symbol
RW
DUi
After Reset
XX11 1111b
NOTE:
1. The contents of registers IDB0 and IDB1 are transferred to the three-phase output shift register by the transfer trigger. After the
transfer trigger occurs, the values written in the IDB0 register determine the first phase output signals. Then, the values written in the
IDB1 register at the falling edge of the timer A1, A2 and A4 one-shot pulses determine the next phase output signals.
DUBi
DVi
DVBi
DWi
RW
DWBi
RW
(b7-b6)
RW
b7 b6 b5 b4
b1
b2
b3
b0
Bit Name
U-phase output buffer i
V-phase output buffer i
W-phase output buffer i
Function
Set output levels.
0: Active level
1: Inactive level
When read, the contents of the three-phase
shift register can be read.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined
U-phase output buffer i
W-phase output buffer i