
22.3.1
CAN1 Wake-Up Interrupt
When a signal applied to the CAN1WU pin is at the falling edge, the CAN1WUR bit in the IIO5IR register
becomes 1 (interrupt requested), regardless of the value of the SLEEP bit in the C1SLPR register.
When P7_7 (CAN0IN) is used as a CAN0 input port, the CAN0 wake-up interrupt becomes available by using
event counter mode of TA3IN that shares a pin with CAN0.
When P8_3 (CAN0IN/CAN1IN) is used as a CAN input port, the CAN0 and CAN1 wake-up interrupts become
available by using INT1 that shares a pin with CAN0IN/CAN1IN.
22.3.2
CANmj Interrupt
The followings are the CANmj interrupt request sources. (m = 0, 1, j = 0 to 2)
CANm message slot k (k = 0 to 15) transmit operation completed
CANm message slot k receive operation completed
CANm bus error detected
CANm error-passive state entered
CANm bus-off state entered
When the INTSEL bit in the CmCTLR1 register is set to 0, the result of logical sum of interrupt requests from
the above five sources becomes the CANmj interrupt request.
When the INTSEL bit is set to 1, the interrupt requests from three types of CANmj interrupt request sources,
which are CANm message slot k transmit operation completed, CANm message slot k receive operation
completed, and CANm error (bus error detected, error-passive state entered, and bus-off state entered), are
individually output.
22.3.2.1
When the INTSEL Bit is Set to 0 (output CAN interrupt request via OR gate)
When the INTSEL bit is set to 0 (output CAN interrupt request via OR gate), all the CANm0, CANm1, and
CANm2 interrupt requests are generated by any of the CANmj interrupt source.
Table 22.5 lists interrupt sources and the corresponding interrupt registers (when the INTSEL bit is set to 0).
Figure 22.42 shows a CANmj interrupt block diagram (when the INTSEL bit is set to 0).
When a CANmj interrupt request is generated, the interrupt status bit (the corresponding bit in the CmSISTR
register or CmEISTR register) becomes 1 (interrupt requested). And then, if the interrupt mask bit (the
corresponding bit in the CmSIMKR register or CmEIMKR register) is set to 1 (interrupt request enabled), all
the corresponding CANmjR bits in the IIOnIR register (n = 9, 10, 11 when m = 0, n = 0, 1, 5 when m = 1)
become 1 (interrupt requested).
NOTE:
1. The interrupt status bits in registers CmSISTR and CmEISTR are not cleared to 0 automatically even if an
interrupt is acknowledged. Set each bit to 0 by program.
While any of these status bits whose interrupt is enabled remains 1, the CANmjR bit does not become 1
(interrupt requested) even if another CANmj interrupt request is generated.