
10. Interrupts
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require
the longest time (a), which is at the maximum of 40 cycles.
When the divisor is in the memory, the value below is added.
Normal addressing: 2 + X
Indirect addressing: 5 + X + 2Y
X is the number of wait states for a divisor space. Y is the number of wait states for the space that stores indirect
addresses. If X and Y are in an odd address or in a space using 8-bit bus, the X and Y value must be doubled.
Add one cycle, when above addressing modes are modified by the INDEX instructions.
Table 10.5
Interrupt Sequence Execution Time
NOTE:
1. The value when interrupt vectors are allocated in even addresses in the internal ROM.
10.6.5
IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, the priority level for the acknowledged interrupt
becomes the IPL level.
Software interrupts and special interrupts have no interrupt priority level. If an interrupt request that has no
interrupt priority level is acknowledged, the value shown in
Table 10.6 becomes the IPL level as the interrupt
priority level.
Table 10.6
Interrupts without Interrupt Priority Levels and IPL
Interrupts
Double-speed mode
Single-speed mode
23 cycles
14 cycles
14 cycles
9 cycles
NMI
Watchdog timer
Undefined instruction
Address match
14 cycles
9 cycles
Overflow
19 cycles
14 cycles
BRK instruction (relocatable vector tabl
e)(1)24 cycles
17 cycles
BRK instruction (fixed vector table)
26 cycles
19 cycles
High-speed interrupt
7 cycles
5 cycles
Interrupt Source
IPL level
Watchdog timer, NMI, DMACII end-of-transfer interrupt, oscillation stop detection
7
Software, address match
Not changed