![](http://datasheet.mmic.net.cn/30000/M30956FKTGP_datasheet_2359453/M30956FKTGP_33.png)
1. Overview
1.4
Pin Assignments
Figure 1.3
Pin Assignment for 144-pin Package
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
M32C/95 Group
(M32C/95T)
IIO0_0 / IIO1_0 / P1_0
AN0_7 / P0_7
AN0_6 / P0_6
AN0_5 / P0_5
AN0_4 / P0_4
P11_4
IIO1_3 / P11_3
IIO1_2 / P11_2
IIO1_1 / P11_1
IIO1_0 / P11_0
AN0_3 / P0_3
AN0_2 / P0_2
AN0_1 / P0_1
AN0_0 / P0_0
AN15_7 / CTS6 / RTS6 / IIO0_7 / P15_7
AN15_6 / CLK6 / IIO0_6 / P15_6
AN15_5 / RXD6 / IIO0_5 / P15_5
AN15_4 / TXD6 / IIO0_4 / P15_4
AN15_3 / CTS5 / RTS5 / IIO0_3 / P15_3
AN15_2 / RXD5 / IIO0_2 / P15_2
AN15_1 / CLK5 / IIO0_1 / P15_1
AN15_0 / TXD5 / IIO0_0 / P15_0
VSS
VCC
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AN_0 / P10_0
AVSS
AVCC
VREF
ADTRG / RXD4 / SCL4 / STXD4 / P9_7
A
N
EX1
/TX
D4
/
SD
A
4
/
S
R
XD
4
/C
A
N1O
U
T
/P
9_6
AN
EX
0
/
C
L
K4
/C
A
N
1
IN
/C
A
N
1
W
U
/
P
9_5
DA
1
/
T
B
4
IN
/
CT
S
4
/
RT
S
4
/S
S
4
/
P
9
_
4
DA
0
/
T
B
3
IN
/
CT
S
3
/
RT
S
3
/S
S
3
/
P
9
_
3
TB2
IN
/
TXD
3
/SD
A3
/
SR
X
D
3
/
P
9_2
TB1
IN
/
R
X
D
3
/
SC
L
3
/
S
T
X
D
3
/
P
9_1
T
B
0I
N
/
C
L
K3
/
P
9_0
IN
T8
/
P14_6
IN
T7
/
P14_5
IN
T6
/
P14_4
II
O
1
_
7
/
P14_3
II
O
1
_
6
/
P14_2
II
O
1
_
5
/
P14_1
II
O
1
_
4
/
P14_0
BY
T
E
CN
V
S
XC
IN
/
P
8_7
XC
OU
T
/
P
8_6
RE
SET
XO
U
T
VS
S
XI
N
VC
C
N
M
I/
P
8_5
IN
T2
/
P
8_4
C
A
N
0
IN
/
C
A
N
1
IN
/
IN
T1
/
P
8_3
C
A
N
0
O
U
T
/C
A
N
1
O
U
T
/
IN
T0
/
P
8_2
TA4I
N
/
U
/C
T
S5
/
R
T
S
5
/I
IO1
_5
/U
D
0
B
/
U
D
1
B
/
P
8_1
T
A
4OU
T
/U
/
R
X
D
5
/
U
D
0
A
/U
D
1
A
/
P
8_0
C
A
N
0
IN
/TA3I
N
/
C
L
K
5
/
II
O1
_4
/
U
D
0
B
/U
D
1
B
/
P
7_7
C
A
N
0
O
U
T
/
TA3
O
U
T
/
TXD
5
/I
IO1
_3
/U
D
0
A
/
U
D
1
A
/
P
7_6
T
A
2
IN
/
W
/
R
X
D
6
/II
O
1
_
2
/
P
7_5
TA
2
O
U
T
/
W
/
TX
D
6
/II
O
1
_
1
/
P
7_4
T
A
1
IN
/V
/
C
T
S2
/
R
T
S2
/
SS2
/II
O
1
_
0
/
P
7_3
T
A
1O
U
T
/
V
/
C
L
K
2
/
P7
_
2
TB5I
N
/
TA0
IN
/
R
X
D
2
/
SC
L
2
/STX
D
2
/II
O
1
_
7
/
P
7_1
P4_3
VC
C
P4_2
P4_1
P4_0
VS
S
P3_7
/TA4
IN
/
U
P3_6/
TA4
O
U
T
/U
P3_5/
TA2
IN
/W
P3_4
/TA2
O
U
T
/
W
P3_3
/TA1
IN
/
V
P3_2
/TA1
O
U
T
/
V
P
3
_
1
/
U
D
0
B
/
U
D
1
B
/
T
A
3
O
U
T
P
3
_
0
/
U
D
0
A
/
U
D
1
A
/
T
A
0
O
U
T
P
2
_
7
/
A
N
2
_
7
P
2
_
6
/
A
N
2
_
6
P
2
_
5
/
A
N
2
_
5
P
2
_
4
/
A
N
2
_
4
V
S
V
C
P
1
2
_
0
P
1
2
_
1
P
1
2
_
2
P
1
2
_
3
P
1
2
_
4
P
2
_
3
/
A
N
2
_
3
P
2
_
2
/
A
N
2
_
2
P
2
_
1
/
A
N
2
_
1
P
2
_
0
/
A
N
2
_
0
P
1
_
1
/
II
O
0
_
1
/
II
O
1
_
1
P
1
_
2
/
II
O
0
_
2
/
II
O
1
_
2
P
1
_
3
/
II
O
0
_
3
/
II
O
1
_
3
P
1
_
4
/
II
O
0
_
4
/
II
O
1
_
4
P
1
_
5
/
IN
T
3
/
II
O
0
_
5
/
II
O
1
_
5
P
1
_
6
/
IN
T
4
/
II
O
0
_
6
/
II
O
1
_
6
P
1
_
7
/
IN
T
5
/
II
O
0
_
7
/
II
O
1
_
7
P7_0
P6_7 / TXD1 / SDA1 / SRXD1
VCC
P6_6 / RXD1 / SCL1 / STXD1
VSS
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / RXD0 / SCL0 / STXD0
P6_1 / CLK0 / CAN2IN / CAN2WU
P6_0 / CTS0 / RTS0 / SS0 / CAN2OUT
P13_7
P13_6
P13_5
P13_4
P5_7
P5_6
P5_5
P5_4
P13_3
VSS
P13_2
VCC
P13_1
P13_0
P5_3 / CLKOUT
P5_2
P5_1
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
P4_4
AN_4 / KI0 / P10_4
NOTES:
1. TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6
2. P7_0 and P7_1 are N-channel open drain output.
3. Refer to Package Dimensions for the pin 1 position on the package.
PLQP0144KA-A
(144P6Q-A)
(top view)
(1,2)
(note 3)
(2
)