
12. DMAC
A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request
source. Bits DSEL 4 to DSEL0 in the DMiSL register determine what source is selected. When a software trigger is
selected, a DMA transfer is started by setting the DSR bit in the DMiSL register to 1. When an interrupt request
generated by individual peripheral functions is selected, a DMA transfer is started by an interrupt request occurrence.
Unlike other interrupt requests, the I flag and interrupt control register do not affect a DMA transfer. A DMA request
can be acknowledged even if an interrupt is disabled or an interrupt request cannot be acknowledged for other reasons.
The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Table 12.1
DMAC Specifications
NOTE:
1. The IR bit in the interrupt control register does not change when a DMA request is acknowledged.
Item
Specification
Channels
4 channels (cycle-steal method)
Transfer memory space
From a given address in a 16-Mbyte space to a fixed address in a 16-Mbyte space
From a fixed address in a 16-Mbyte space to a given address in a 16-Mbyte space
Maximum bytes transferred
128 Kbytes (when a 16-bit data is transferred) or 64 Kbytes (when an 8-bit data is
transferred)
Falling edge or both edges of signals applied to pins INT0 to INT3
INT6 to INT8 pins interrupt request
Timer A0 to A4 interrupt requests
Timer B0 to B5 interrupt requests
UART0 to UART6 transmit and receive interrupt requests
A/D0 conversion interrupt request
Intelligent I/O interrupt request
CAN interrupt request
Software trigger
Channel priority
DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority)
Transfer unit
8 bits, 16 bits
Transfer address
Fixed address: one specified address
Incremented address: address which is incremented by the transfer unit on each
successive access.
(Source address and destination address cannot be both fixed nor both
incremented.)
Transfer
mode
Single transfer
Transfer is completed when the DCTi register (i = 0 to 3) is set to 0000h
Repeat transfer
When the DCTi register is set to 0000h, values of the DRCi register are reloaded
into the DCTi register and a DMA transfer is continued
DMA interrupt request
generation timing
When the DCTi register changes 0001h to 0000h, a DMA interrupt request is
generated
DMA startup Single transfer
DMAC starts a data transfer when a DMA request is generated after bits MDi1 and
MDi0 in the DMDj register (j = 0 to 1) are set to 01b (single transfer), while the DCTi
register is set to 0001h or higher value
Repeat transfer
DMAC starts a data transfer when a DMA request is generated after bits MDi1 and
MDi0 are set to 11b (repeat transfer), while the DCTi register is set to 0001h or
higher value
DMA stop
Single transfer
DMAC stops when bits MDi1 and MDi0 are set to 00b (DMA disabled). Or when
the DCTi register is set to 0000h (0 DMA transfer) by a DMA transfer or writing
Repeat transfer
DMA stops when bits MDi1 and MDi0 are set to 00b. Or when the DCTi register is
set to 0000h by a DMA transfer or writing, and the DRCi register is set to 0000h
Reload timing to registers DCTi
and DMAi
Values are reloaded when the DCTi register changes from 0001h to 0000h in
repeat transfer mode
DMA transfer time
Minimum 3 bus clocks between SFR area and internal RAM