
23. 32-Slot CAN Module
23.1.13 CAN2 Slot Interrupt Mask Register (C2SIMKR Register)
Figure 23.16
C2SIMKR Register
Symbol
Address
After Reset(2)
RW
CAN2 Slot Interrupt Mask Register(1)
C2SIMKR
0513h - 0510h
00000000h
Function
Bit Symbol
Bit Name
Message slot 31
interrupt request mask bit
SIM30
NOTE:
1. Set the C2SIMKR register while the C2MCTLi (i = 0 to 31) register, corresponding to the bit to be changed, is set to 00h.
2
. The value is obtained by setting the SLEEP bit in the C2SLPR register to 1 (sleep mode exited) after reset and supplying
the clock to the CAN module.
SIM31
b23
b24
b31
b16
b7
b8
b15
b0
Message slot 30
interrupt request mask bit
RW
Message slot 29
interrupt request mask bit
SIM28
SIM29
Message slot 28
interrupt request mask bit
Message slot 27
interrupt request mask bit
SIM26
SIM27
Message slot 26
interrupt request mask bit
Message slot 25
interrupt request mask bit
SIM24
SIM25
Message slot 24
interrupt request mask bit
Message slot 23
interrupt request mask bit
SIM22
SIM23
Message slot 22
interrupt request mask bit
Message slot 21
interrupt request mask bit
SIM20
SIM21
Message slot 20
interrupt request mask bit
Message slot 19
interrupt request mask bit
SIM18
SIM19
Message slot 18
interrupt request mask bit
Message slot 17
interrupt request mask bit
SIM16
SIM17
Message slot 16
interrupt request mask bit
RW
Message slot 15
interrupt request mask bit
SIM14
SIM15
Message slot 14
interrupt request mask bit
RW
Message slot 13
interrupt request mask bit
SIM12
SIM13
Message slot 12
interrupt request mask bit
Message slot 11
interrupt request mask bit
SIM10
SIM11
Message slot 10
interrupt request mask bit
Message slot 9
interrupt request mask bit
SIM8
SIM9
Message slot 8
interrupt request mask bit
Message slot 7
interrupt request mask bit
SIM6
SIM7
Message slot 6
interrupt request mask bit
Message slot 5
interrupt request mask bit
SIM4
SIM5
Message slot 4
interrupt request mask bit
Message slot 3
interrupt request mask bit
SIM2
SIM3
Message slot 2
interrupt request mask bit
Message slot 1
interrupt request mask bit
SIM0
SIM1
Message slot 0
interrupt request mask bit
RW
Controls whether the
interrupt request of the
corresponding message slot
is enabled or masked.
0: Interrupt request masked
(disabled)
1: Interrupt request enabled