
1. Overview
Figure 1.4
Pin Assignment for 100-Pin Package
PLQP0100KB-A
(100P6Q-A)
(top view)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IIO1_0 / IIO0_0 / P1_0
AN0_7 / P0_7
AN0_6 / P0_6
AN0_5 / P0_5
AN0_4 / P0_4
AN0_3 / P0_3
AN0_2 / P0_2
AN0_1 / P0_1
AN0_0 / P0_0
AN_7 / KI3 / P10_7
AN_6 / KI2 / P10_6
AN_5 / KI1 / P10_5
AN_4 / KI0 / P10_4
AN_3 / P10_3
AN_2 / P10_2
AN_1 / P10_1
AN_0 / P10_0
AVSS
AVCC
VREF
ADTRG / RXD4 / SCL4 / STXD4 / P9_7
D
A
1
/
T
B
4
IN
/
C
T
S
4
/
R
T
S
4
/
S
4
/
P
9
_
4
D
A
0
/
T
B
3
IN
/
C
T
S
3
/
R
T
S
3
/
S
3
/
P
9
_
3
T
B
2
IN
/
T
X
D
3
/
S
D
A
3
/
S
R
X
D
3
/
P
9
_
2
T
B
1
IN
/
R
X
D
3
/
S
C
L
3
/
S
T
X
D
3
/
P
9
_
1
T
B
0
IN
/
C
L
K
3
/
P
9
_
0
B
Y
T
E
C
N
V
S
X
C
IN
/
P
8
_
7
X
C
O
U
T
/
P
8
_
6
R
E
S
E
T
X
O
U
T
V
S
X
IN
V
C
N
M
I
/
P
8
_
5
IN
T
2
/
P
8
_
4
C
A
N
0
IN
/
C
A
N
1
IN
/
IN
T
1
/
P
8
_
3
C
A
N
0
O
U
T
/
C
A
N
1
O
U
T
/
IN
T
0
/
P
8
_
2
T
A
4
IN
/
U
/
C
T
S
5
/
R
T
S
5
/
II
O
1
_
5
/
U
D
0
B
/
U
D
1
B
/
P
8
_
1
T
A
4
O
U
T
/
U
/
R
X
D
5
/
U
D
0
A
/
U
D
1
A
/
P
8
_
0
C
A
N
0
IN
/
T
A
3
IN
/
C
L
K
5
/
II
O
1
_
4
/
U
D
0
B
/
U
D
1
B
/
P
7
_
7
C
A
N
0
O
U
T
/
T
A
3
O
U
T
/
T
X
D
5
/
II
O
1
_
3
/
U
D
0
A
/
U
D
1
A
/
P
7
_
6
T
A
2
IN
/
W
/
R
X
D
6
/
II
O
1
_
2
/
P
7
_
5
T
A
2
O
U
T
/
W
/
T
X
D
6
/
II
O
1
_
1
/
P
7
_
4
T
A
1
IN
/
V
/
C
T
S
2
/
R
T
S
2
/
S
2
/
II
O
1
_
0
/
P
7
_
3
P7_2 / TA1OUT / V / CLK2
P7_1 / TB5IN / TA0IN / RXD2 / SCL2 / STXD2 / IIO1_7
P
4
_
1
P
4
_
0
P
3
_
7
/
T
A
4
IN
/
U
P
3
_
6
/
T
A
4
O
U
T
/
U
P
3
_
5
/
T
A
2
IN
/
W
P
3
_
4
/
T
A
2
O
U
T
/
W
P
3
_
3
/
T
A
1
IN
/
V
P
3
_
2
/
T
A
1
O
U
T
/
V
P
3
_
1
/
U
D
0
B
/
U
D
1
B
/
T
A
3
O
U
T
P
3
_
0
/
U
D
1
A
/
U
D
0
A
/
T
A
0
O
U
T
P
2
_
7
/
A
N
2
_
7
P
2
_
6
/
A
N
2
_
6
P
2
_
5
/
A
N
2
_
5
P
2
_
4
/
A
N
2
_
4
V
S
V
C
P
2
_
3
/
A
N
2
_
3
P
2
_
2
/
A
N
2
_
2
P
2
_
1
/
A
N
2
_
1
P
2
_
0
/
A
N
2
_
0
IIO1_1 / IIO0_1 / P1_1
IIO1_2 / IIO0_2 / P1_2
P
1
_
3
/
II
O
0
_
3
/
II
O
1
_
3
P
1
_
4
/
II
O
0
_
4
/
II
O
1
_
4
P
1
_
5
/
IN
T
3
/
II
O
0
_
5
/
II
O
1
_
5
P
1
_
6
/
IN
T
4
/
II
O
0
_
6
/
II
O
1
_
6
P
1
_
7
/
IN
T
5
/
II
O
0
_
7
/
II
O
1
_
7
P7_0 / TA0OUT / TXD2 / SDA2 / SRXD2 / IIO1_6
P6_7 /TXD1 / SDA1 / SRXD1
P6_6 / RXD1 / SCL1 / STXD1
P6_5 / CLK1
P6_4 / CTS1 / RTS1 / SS1
P6_3 / TXD0 / SDA0 / SRXD0
P6_2 / RXD0 / SCL0 / STXD0
P6_1 / CLK0 / CAN2IN / CAN2WU
P6_0 / CTS0 / RTS0 / SS0 / CAN2OUT
P5_7
P5_6
P5_5
P5_4
P5_3 / CLKOUT
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
ANEX1 / TXD4 / SDA4 / SRXD4 / CAN1OUT / P9_6
ANEX0 / CLK4 / CAN1IN / CAN1WU / P9_5
26
27
28
29
30
P4_3
P4_2
NOTES:
1. P7_0 and P7_1 are N-channel open drain output.
2. Refer to Package Dimensions for the pin 1 position on the package.
(1)
(note2)
M32C/95 Group
(M32C/95T)