參數(shù)資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數(shù): 99/119頁
文件大小: 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
70
06/04/02 Revision 1.07
14.1.23
I/O Base Address Upper 16-bits Register – Offset 30h
Bit
Function
Type
Description
15:0
I/O Base
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit bottom address of an
address range for the bridge to determine when to forward I/O
transactions from one interface to the other.
Reset to 0
14.1.24
I/O Limit Address Upper 16-bits Register – Offset 30h
Bit
Function
Type
Description
31:0
I/O Limit
Address, Upper
16-bits [31:16]
R/W
Defines the upper 16-bits of a 32-bit top address of an address
range for the bridge to determine when to forward I/O
transactions from one interface to the other.
Reset to 0
14.1.25
ECP Pointer Register – Offset 34h
Bit
Function
Type
Description
7:0
Enhanced
Capabilities
Port Pointer
R/O
Enhanced capabilities port offset pointer. Read as B0h to
indicate that the first item resides at that configuration offset.
14.1.26
Bridge Control Register – Offset 3Ch
Bit
Function
Type
Description
16
Parity Error
Response
R/W
Controls the bridge’s response to parity errors on the
secondary interface.
0: ignore address and data parity errors on the secondary
interface
1: enable parity error reporting and detection on the secondary
interface
Reset to 0
17
S1_SERR#
enable
R/W
Controls the forwarding of S1_SERR# or S2_SERR# to the
primary interface.
0: disable the forwarding of S1_SERR# or S2_SERR# to
primary interface
1: enable the forwarding of S1_SERR# or S2_SERR# to
primary interface
Reset to 0
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