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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 52/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
28
06/04/02 Revision 1.07
After the PI7C7300 makes 2
24 (default) attempts of the same delayed write trans-
action on the target bus, PI7C7300 asserts P_SERR# if the SERR# enable bit (bit 8
of command register for secondary bus S1 or S2) is set and the delayed-write-non-
delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event
disable register (offset 64h). PI7C7300 will report system error. See Section 7.4 for
a description of system error conditions.
4.9.3.2
Posted Write Target Termination Response
When PI7C7300 initiates a posted write transaction, the target termination cannot
be passed back to the initiator. Table 4–8 shows the response to each type of target
termination that occurs during a posted write transaction.
TABLE 4-8. RESPONSE TO POSTED WRITE TARGET TERMINATION
Target Termination
Repsonse
Normal
No additional action.
Target Retry
Repeating write transaction to target.
Target Disconnect
Initiate write transaction for delivering remaining posted write data.
Target Abort
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary
status register.
Note that when a target retry or target disconnect is returned and posted write
data associated with that transaction remains in the write buffers, PI7C7300 initiates
another write transaction to attempt to deliver the rest of the write data. If there is
a target retry, the exact same address will be driven as for the initial write trans-action
attempt. If a target disconnect is received, the address that is driven on a
subsequent write transaction attempt will be updated to reflect the address of the
current DWORD. If the initial write transaction is Memory-Write-and-Invalidate
transaction, and a partial delivery of write data to the target is performed before
a target disconnect is received, PI7C7300 will use the memory write command to
deliver the rest of the write data. It is because an incomplete cache line will be
transferred in the subsequent write transaction attempt.
After the PI7C7300 makes 2
24 (default) write transaction attempts and fails to deliver all
posted write data associated with that transaction, PI7C7300 asserts P_SERR# if the
primary SERR# enable bit is set (bit 8 of command register for secondary bus S1 or
S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the
bit 2 of P_SERR# event disable register (offset 64h). PI7C7300 will report system
error. See Section 7.4 for a discussion of system error conditions.
4.9.3.3
Delayed Read Target Termination Response
When PI7C7300 initiates a delayed read transaction, the abnormal target responses
can be passed back to the initiator. Other target responses depend on how much data
the initiator requests. Table 4–9 shows the response to each type of target termination
that occurs during a delayed read transaction.
PI7C7300 repeats a delayed read transaction until one of the following conditions is
met:
§
PI7C7300 completes at least one data transfer.
§
PI7C7300 receives a master abort.
§
PI7C7300 receives a target abort.
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