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參數資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數： | 29/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
7
06/04/02 Revision 1.07
3.3
Secondary Bus Interface Signals (continued)
Name
Pin #
Type
Description
S1_SERR#,
S2_SERR#
K20,
C4
PI
Secondary System Error (Active LOW). Can be
driven LOW by any device to indicate a system
error condition.
S1_REQ#[7:0],
S2_REQ#[6:0]
B11, A12, D13,
C13, C15, A16,
C17, B17
R3, P2, P1, M2,
M1, K1, K3
PIU
Secondary Request (Active LOW). This is
asserted by an external device to indicate that it
wants to start a transaction on the secondary bus.
The input is externally pulled up through a resistor
to VDD.
S1_GNT#[7:0]
S2_GNT#[6:0]
C11, B12, B13,
A14, D14, B16,
D16, B18
P4, R1, N4, M3,
L4, L1, K2
PO
Secondary Grant (Active LOW). PI7C7300
asserts this pin to access the secondary bus.
PI7C7300 de-asserts this pin for at least 2 PCI
clock cycles before asserting it again. During idle
and S1_GNT# or S2-GNT# asserted, PI7C7300 will
drive S1_AD, S1_CBE, and S1_PAR or S2_AD,
S2_CBE, and S2_PAR.
S1_RESET#,
S2_RESET#
B10,
T4
PO
Secondary RESET (Active LOW). Asserted when
any of the following conditions are met:
1.
Signal P_RESET# is asserted.
2.
Secondary reset bit in bridge control register
in configuration space is set.
When asserted, all control signals are tri-stated
and zeroes are driven on S1_AD, S1_CBE, and
S1_PAR or S2_AD, S2_CBE, and S2_PAR.
S1_EN,
S2_EN
W3,
W4
PIU
Secondary Enable (Active HIGH). When S1_EN
or S2_EN is inactive, secondary bus PCI S1 or PCI
S2 will be asynchronously tri-stated.
S1_M66EN,
S2_M66EN
D7,
W5
PI
Secondary Interface 66MHz Operation. This
input is used to specify if PI7C7300 is capable of
running at 66MHz on the secondary side. When
HIGH, the S1 or S2 bus may run at 66MHz. When
LOW, the S1 or S2 bus may only run at 33MHz.
If P_M66EN is pulled LOW, both S1_M66EN and
S2_M66EN need to be LOW.
S_CFN#
Y2
PIU
Secondary Bus Central Function Control Pin.
When tied LOW, it enables the internal arbiter.
When tied HIGH, an external arbiter must be used.
S1_REQ#[0] or S2_REQ#[0] is reconfigured to be
the secondary bus grant input, and S1_GNT#[0] or
S2_GNT#[0] is reconfigured to be the secondary
bus request output.
3.4
Clock Signals
Name
Pin #
Type
Description
P_CLK
V6
PI
Primary Clock Input. Provides timing for all
transactions on the primary interface.
S1_CLKOUT
[7:0]
A11, C12, A13,
B14, B15, C16,
A18, A19
PTS
Secondary Clock Output. Provides secondary 1
clocks phase synchronous with the P_CLK.
S2_CLKOUT
[7:0]
T3, T1, P3, N3,
M4, L3, L2, J1
PTS
Secondary Clock Output. Provides secondary 2
clocks phase synchronous with the P_CLK.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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