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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 44/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
20
06/04/02 Revision 1.07
4.7.6
Delayed Read Completion on Initiator Bus
When the transaction has been completed on the target bus, and the delayed read
data is at the head of the read data queue, and all ordering constraints with posted
write transactions have been satisfied, the PI7C7300 transfers the data to the initiator
when the initiator repeats the transaction. For memory read transactions, PI7C7300
aliases the memory read, memory read line, and memory read multiple bus
commands when matching the bus command of the transaction to the bus command
in the delayed transaction queue. PI7C7300 returns a target disconnect along with the
transfer of the last DWORD of read data to the initiator. If PI7C7300 initiator terminates
the transaction before all read data has been transferred, the remaining read data left
in data buffers is discarded.
When the master repeats the transaction and starts transferring prefetchable read
data from data buffers while the read transaction on the target bus is still in progress
and before a read boundary is reached on the target bus, the read transaction starts
operating in flow-through mode. Because data is flowing through the data buffers from
the target to the initiator, long read bursts can then be sustained. In this case, the read
transaction is allowed to continue until the initiator terminates the trans-action, or until
an aligned 4KB address boundary is reached, or until the buffer fills, whichever comes
first. When the buffer empties, PI7C7300 reflects the stalled condition to the initiator by
disconnecting the initiator with data. The initiator may retry the transaction later if data
are needed. If the initiator does not need any more data, the initiator will not continue
the disconnected transaction. In this case, PI7C7300 will start the master timeout
timer. The remaining read data will be discarded after the master timeout timer
expires. To provide better latency, if there are any other pending data for other
transactions in the RDB (Read Data Buffer), the remaining read data will be discarded
even though the master timeout timer has not expired.
PI7C7300 implements a master timeout timer that starts counting when the delayed
read completion is at the head of the delayed transaction queue, and the read data is
at the head of the read data queue. The initial value of this timer is program-mable
through configuration register. If the initiator does not repeat the read transaction and
before the master timeout timer expires (2
15 default), PI7C7300 discards the read
transaction and read data from its queues. PI7C7300 also conditionally asserts
P_SERR# (see Section 7.4).
PI7C7300 has the capability to post multiple delayed read requests, up to a maximum
of four in each direction. If an initiator starts a read transaction that matches the
address and read command of a read transaction that is already queued, the current
read
command
is
not
posted
as
it
is
already
contained
in
the delayed transaction queue.
See Section 6 for a discussion of how delayed read transactions are ordered
when crossing PI7C7300.
4.7.7
Fast Back-to-Back Read Transaction
PI7C7300 can recognize fast back-to-back read transaction
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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