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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 79/119頁(yè) |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
52
06/04/02 Revision 1.07
When the target resides on another PCI bus, the master must acquire not only the lock
on its own PCI bus but also the lock on every bus between its bus and the target’s bus.
When PI7C7300 detects on the primary bus, an initial locked transaction intended for a
target on the secondary bus, PI7C7300 samples the address, transaction type, byte
enable bits, and parity, as described in Section 4.6.4. It also samples the lock signal. If
there is a lock established between 2 ports or the target bus is already locked by
another master, then the current lock cycle is retried without forward. Because a target
retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus,
and therefore the lock is not yet established.
The first locked transaction must be a memory read transaction. Subsequent locked
transactions can be memory read or memory write transactions. Posted memory write
transactions that are a part of the locked transaction sequence are still posted.
Memory read transactions that are a part of the locked transaction sequence are not
pre-fetched.
When the locked delayed memory read request is queued, PI7C7300 does not queue
any more transactions until the locked sequence is finished. PI7C7300 signals a target
retry to all transactions initiated subsequent to the locked read transaction that are
intended for targets on the other side of PI7C7300. PI7C7300 allows any transactions
queued before the locked transaction to complete before initiating the locked
transaction.
When the locked delayed memory read request transaction moves to the head of the
delayed transaction queue, PI7C7300 initiates the transaction as a locked read
transaction by de-asserting LOCK# on the target bus during the first address phase,
and by asserting LOCK# one cycle later. If LOCK# is already asserted (used by
another initiator), PI7C7300 waits to request access to the secondary bus until LOCK#
is de-asserted when the target bus is idle. Note that the existing lock on the target bus
could not have crossed PI7C7300. Otherwise, the pending queued locked transaction
would not have been queued. When PI7C7300 is able to complete a data transfer with
the locked read transaction, the lock is established on the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the
same address, transaction type, and byte enable bits, PI7C7300 transfers the read
data back to the initiator, and the lock is then also established on the primary bus.
For PI7C7300 to recognize and respond to the initiator, the initiator’s subsequent
attempts of the read transaction must use the locked transaction sequence (de-
assert LOCK# during address phase, and assert LOCK# one cycle later). If the LOCK#
sequence is not used in subsequent attempts, a master timeout condition may result.
When a master timeout condition occurs, SERR# is conditionally asserted (see
Section 7.4), the read data and queued read transaction are discarded, and the
LOCK# signal is de-asserted on the target bus.
Once the intended target has been locked, any subsequent locked transactions
initiated on the initiator bus that are forwarded by PI7C7300 are driven as locked
transactions on the target bus.
The first transaction to establish LOCK# must be Memory Read. If the first transaction
is not Memory read, the following transactions behave accordingly:
- Type 0 Configuration Read/Write induces master abort
- Type 1 Configuration Read/Write induces master abort
- I/O Read induces master abort
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
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