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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 28/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
6
06/04/02 Revision 1.07
3.3
Secondary Bus Interface Signals (continued)
Name
Pin #
Type
Description
S1_PAR,
S2_PAR
K18,
B4
PB
Secondary Parity. Parity is even across
S1_AD[31:0], S1_CBE[3:0], and S1_PAR or
S2_AD[31:0], S2_CBE[3:0], and S2_PAR (i.e. an
even number of 1’s). S1_PAR or S2_PAR is an
input and is valid and stable one cycle after the
address phase (indicated by assertion of
S1_FRAME# or S2_FRAME#) for address parity.
For write data phases, S1_PAR or S2_PAR is an
input and is valid one clock after S1_IRDY#
S2_IRDY# is asserted. For read data phase,
S1_PAR or S2_PAR is an output and is valid one
clock after S1_TRDY# or S2_TRDY# is asserted.
Signal S1_PAR or S2_PAR is tri-stated one cycle
after the S1_AD or S2_AD lines are tri-stated.
During bus idle, PI7C7300 drives S1_PAR or
S2_PAR to a valid logic level when the internal
grant is asserted.
S1_FRAME#,
S2_FRAME#
H20,
D2
PSTS
Secondary FRAME (Active LOW). Driven by the
initiator of a transaction to indicate the beginning
and duration of an access. The de-assertion of
S1_FRAME# or S2_FRAME# indicates the final
data phase requested by the initiator. Before
being tri-stated, it is driven to a de-asserted state
for one cycle.
S1_IRDY#,
S2_IRDY#
H19,
B2
PSTS
Secondary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary
side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before
tri-stated, it is driven to a de-asserted state for
one cycle.
S1_TRDY#,
S2_TRDY#
H18,
A2
PSTS
Secondary TRDY (Active LOW). Driven by the
target of a transaction to indicate its ability to
complete current data phase on the secondary
side. Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before
tri-stated, it is driven to a de-asserted state for
one cycle.
S1_DEVSEL#,
S2_DEVSEL#
J20,
D3
PSTS
Secondary Device Select (Active LOW).
Asserted by the target indicating that the device is
accepting the transaction. As a master,
PI7C7300 waits for the assertion of this signal
within 5 cycles of S1_FRAME# or S2_FRAME#
assertion; otherwise, terminate with master abort.
Before tri-stated, it is driven to a de-asserted state
for one cycle.
S1_STOP#,
S2_STOP#
J19,
C3
PSTS
Secondary STOP (Active LOW). Asserted by
the target indicating that the target is requesting
the initiator to stop the current transaction. Before
tri-stated, it is driven to a de-asserted state for
one cycle.
S1_LOCK#,
S2_LOCK#
J18,
B3
PSTS
Secondary LOCK (Active LOW). Asserted by
the master for multiple transactions to complete.
S1_PERR#,
S2_PERR#
J17,
D4
PSTS
Secondary Parity Error (Active LOW). Asserted
when a data parity error is detected for data
received on the secondary interface. Before
being tri-stated, it is driven to a de-asserted state
for one cycle.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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