- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄190059 > PI7C7300NA (PERICOM SEMICONDUCTOR CORP) PCI BUS CONTROLLER, PBGA272 PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 72/119頁(yè) |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)當(dāng)前第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
46
06/04/02 Revision 1.07
-
The SERR# enable bit is set in the command register.
-
The posted write parity error bit of P_SERR# event disable register is not set.
-
The parity error response bit is set in the bridge control register of the
secondary interface.
-
The parity error response bit is set in the command register of the primary
interface.
-
PI7C7300 has not detected the parity error on the primary (initiator) bus which
the parity error is not forwarded from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR#, the following events occur:
§
PI7C7300 sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
§
PI7C7300 asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register of the
secondary interface.
-
The parity error response bit is set in the command register of the primary
interface.
-
PI7C7300 has not detected the parity error on the secondary (initiator) bus
which the parity error is not forwarded from the secondary bus to the primary
bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator
does not know that the error occurred. Because the data has already been delivered
with no errors, there is no other way to signal this information back to the initiator.
If the parity error has forwarded from the initiating bus to the target bus, P_SERR# will
not be asserted.
7.3
Data Parity Error Reporting Summary
In the previous sections, the responses of PI7C7300 to data parity errors are
presented according to the type of transaction in progress. This section organizes
the responses of PI7C7300 to data parity errors according to the status bits that
PI7C7300 sets and the signals that it asserts.
Table 7–1 shows setting the detected parity error bit in the status register,
corresponding to the primary interface. This bit is set when PI7C7300 detects
a parity error on the primary interface
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC-PROJ2 | SOT-23, Rail-to-Rail Output, Picoamp Input Current Precision Op Amp; Package: SOT; No of Pins: 5; Temperature Range: 0°C to +70°C |
| PIC-TDB | PIC TUTOR/DEV BOARD |
| PIC16C505-20/P | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP14 |
| PIC16C54CT-04I/SO | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO18 |
| PIC16C56A-20I/JW | 8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開(kāi)發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。