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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 50/119頁(yè) |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
26
06/04/02 Revision 1.07
4.9.1
Master Termination Initiated by PI7C7300
PI7C7300, as an initiator, uses normal termination if DEVSEL# is returned by target
within five clock cycles of PI7C7300’s assertion of FRAME# on the target bus. As an
initiator, PI7C7300 terminates a transaction when the following conditions are met:
§
During a delayed write transaction, a single DWORD is delivered.
§
During a non-prefetchable read transaction, a single DWORD is transferred from
the target.
§
During a prefetchable read transaction, a pre-fetch boundary is reached.
§
For a posted write transaction, all write data for the transaction is transferred from
data buffers to the target.
§
For burst transfer, with the exception of “Memory Write and Invalidate”
transactions, the master latency timer expires and the PI7C7300’s bus grant is de-
asserted.
§
The target terminates the transaction with a retry, disconnect, or target abort.
If PI7C7300 is delivering posted write data when it terminates the transaction because
the master latency timer expires, it initiates another transaction to deliver the remaining
write data. The address of the transaction is updated to reflect the address of the
current DWORD to be delivered.
If PI7C7300 is pre-fetching read data when it terminates the transaction because the
master latency timer expires, it does not repeat the transaction to obtain more data.
4.9.2
Master Abort Received by PI7C7300
If the initiator initiates a transaction on the target bus and does not detect DEVSEL#
returned by the target within five clock cycles of the assertion of FRAME#, PI7C7300
terminates the transaction with a master abort. This sets the received-master-abort bit
in the status register corresponding to the target bus.
For delayed read and write transactions, PI7C7300 is able to reflect the master abort
condition back to the initiator. When PI7C7300 detects a master abort in response to a
delayed transaction, and when the initiator repeats the transaction, PI7C7300 does not
respond to the transaction with DEVSEL# which induces the master abort condition
back to the initiator. The transaction is then removed from the delayed transaction
queue. When a master abort is received in response to a posted write transaction,
PI7C7300 discards the posted write data and makes no more attempt to deliver the
data. PI7C7300 sets the received-master-abort bit in the status register when the
master abort is received on the primary bus, or it sets the received master abort bit in
the secondary status register when the master abort is received on the secondary
interface. When master abort is detected in posted write transaction with both master-
abort-mode bit (bit 5 of bridge control register) and the SERR# enable bit (bit 8 of
command register for secondary bus S1 or S2) are set, PI7C7300 asserts P_SERR# if
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