參數資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數: 101/119頁
文件大?。?/td> 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
72
06/04/02 Revision 1.07
14.1.26
Bridge Control Register – Offset 3Ch (continued)
27
Discard Timer
P_SERR#
enable
R/WC
This bit Is set to 1 and P_SERR# is asserted when either the
primary discard timer or the secondary S1 or S2 discard timer
expire.
Reset to 0
31-28
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
14.1.27
Diagnostic / Chip Control Register – Offset 40h
Configuration 1
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control
R/W
Controls when the bridge (as a target) disconnects memory
write transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address
boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
4
Memory Read
Flow-Through
Control
R/W
Controls whether the bridge supports memory read flow-
through
0: Enable
1: Disable
Reset to 0
8:5
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
10:9
Test Mode For
All Counters at
P and S1
R/O
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
15:11
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
Configuration 2
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
1
Memory Write
Disconnect
Control at S2
R/W
Controls when the bridge (as a target) disconnects memory
write transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address
boundary
Reset to 0
3:2
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
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