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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 118/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
88
06/04/02 Revision 1.07
pins and on-chip system logic. The VDD, GND, PLL, AGND, AVDD and JTAG pins are
NOT in the boundary-scan chain.
The boundary-scan register cells are dedicated logic and do not have any system
function. Data may be loaded into the boundary-scan register master cells from
the device input pins and output pin-drivers in parallel by the mandatory sample/
preload and extest instructions. Parallel loading takes place on the rising edge of TCK.
Data may be scanned into the boundary-scan register serially via the TDI serial input
pin, clocked by the rising edge of TCK. When the required data has been loaded into
the master-cell stages, it can be driven into the system logic at input pins or onto the
output pins on the falling edge of TCK state. Data may also be shifted out of the
boundary-scan register by means of the TDO serial output pin at the falling edge of
TCK.
16.6
TAP Controller
The TAP (Test Access Port) controller is a 4-state synchronous finite state machine
that controls the sequence of test logic operations. The TAP can be controlled via a
bus master. The bus master can be either automatic test equipment or a component
(i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in
response to a rising edge of TCK. The value of the test mode state (TMS) input signal
at a rising edge of TCK controls the sequence of state changes. The TAP controller is
initialized after power-up by applying a low to the TRST# pin. In addition, the TAP
controller can be initialized by applying a high signal level on the TMS input for a
minimum of five TCK periods.
For greater detail on the behavior of the TAP controller, test logic in each controller
state and the state machine and public instructions, refer to the IEEE 1149.1 Standard
Test
Access
Port
and
Boundary-Scan
Architecture
document
(available
from the IEEE).
TABLE 16-2. JTAG BOUNDARY REGISTER ORDER
Order
Pin Names
Type
Order
Pin Names
Type
0
ENUM#
output
60
P_STOP#
control
1
ENUM#
control
61
P_PERR#
bidir
2
HS_EN
input
62
P_PERR#
control
3
S_CFN#
input
63
P_LOCK#
input
4
S1_EN
input
64
P_SERR#
output
5
S2_EN
input
65
P_SERR#
control
6
SCAN_TM#
input
66
P_AD[13]
bidir
7
SCAN_EN
67
P_AD[13]
control
8
PLL_TM
input
68
P_AD[14]
bidir
9
BYPASS
input
69
P_AD[14]
control
10
S2_M66EN
input
70
P_AD[11]
bidir
11
P_RESET#
input
71
P_AD[11]
control
12
P_GNT#
input
72
P_AD[15]
bidir
13
P_REQ#
output
73
P_AD[15]
control
14
P_REQ#
control
74
P_AD[12]
bidir
15
P_AD[30]
bidir
75
P_AD[12]
control
16
P_AD[30]
control
76
P_AD[8]
bidir
17
P_AD[31]
bidir
77
P_AD[8]
control
18
P_AD[31]
control
78
P_CBE[1]
bidir
19
P_AD[27]
bidir
79
P_CBE[1]
control
20
P_AD[27]
control
80
P_AD[9]
bidir
21
P_AD[26]
bidir
81
P_AD[9]
control
22
P_AD[26]
control
82
P_AD[5]
bidir
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