參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 84/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
57
06/04/02 Revision 1.07
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at
the last master that used the PCI bus. That is, PI7C7300 keeps the secondary bus
grant asserted to a particular master until a new secondary bus request comes along.
After reset, PI7C7300 parks the secondary bus at itself until transactions start
occurring on the secondary bus. If the internal arbiter is disabled, PI7C7300 parks the
secondary bus only when the reconfigured grant signal, S_REQ#[0], is asserted and
the secondary bus is idle.
10
Compact PCI Hot Swap
Compact PCI (cPCI) Hot Swap (PICMG 2.1, R1.0) defines a process for installing and
removing PCI boards form a Compact PCI system without powering down the system.
The PI7C7300 is Hot Swap Friendly silicon that supports all the cPCI Hot Swap
Capable features and adds support for Software Connection Control. Being Hot Swap
Friendly, the PI7C7300 supports the following:
§
Compliance with PCI Specification 2.2
§
Tolerates VCC from Early Power
§
Asynchronous Reset
§
Tolerates Precharge Voltage
§
I/O Buffers Meet Modified V/I Requirements
§
Limited I/O Pin Leakage at Precharge Voltage
When the PI7C7300 resides on the Compact PCI add-in card, the Primary Bus must
be the bus that is inserted into the Compact PCI system. To perform the Hot Swap
function, the device must be configured according to the CPCI Hot-Swap
Specifications.
For the PI7C7300, the only path for configuration is through the
Primary Bus. The bridge may not be configured through either secondary buses.
If the user chooses to use the secondary buses for insertion, an external register
needs to be provided for the Hot Swap Control Status Register.
11
Clocks
This chapter provides information about the clocks.
11.1
Primary Clock Inputs
PI7C7300 implements a primary clock input for the PCI interface. The primary
interface is synchronized to the primary clock input, P_CLK, and the secondary
interface is synchronized to the secondary clock. The secondary clock is derived
internally from the primary clock, P_CLK, through an internal PLL. PI7C7300 operates
at a maximum frequency of 66 MHz.
11.2
Secondary Clock Outputs
PI7C7300 has 16 secondary clock outputs, S_CLKOUT[15:0] that can be used as
clock inputs for up to fifteen external secondary bus devices. The S_CLKOUT[15:0]
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