參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 66/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
40
06/04/02 Revision 1.07
support delayed transactions are being used in the same system. A fairness
algorithm is used to arbitrate between the posted write queue and the delayed
transaction queue.
6.4
Data Synchronization
Data synchronization refers to the relationship between interrupt signaling and data
delivery. The PCI Local Bus Specification, Revision 2.2, provides the following
alternative methods for synchronizing data and interrupts:
§
The device signaling the interrupt performs a read of the data just written
(software).
§
The device driver performs a read operation to any register in the interrupting
device before accessing data written by the device (software).
§
System hardware guarantees that write buffers are flushed before interrupts are
forwarded.
PI7C7300 does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by
a read operation, either from the device to the location just written (or some other
location along the same path), or from the device driver to one of the device registers.
7
Error Handling
PI7C7300 checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C7300 always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C100
always attempts to be transparent when reporting errors, but this is not always
possible, given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C7300 implements the following:
§
PERR# and SERR# signals on both the primary and secondary interfaces
§
Primary status and secondary status registers
§
The device-specific P_SERR# event disable register
This chapter provides detailed information about how PI7C7300 handles errors.
It also describes error status reporting and error operation disabling.
7.1
Address Parity Errors
PI7C7300 checks address parity for all transactions on both buses, for all address and
all bus commands. When PI7C7300 detects an address parity error on the primary
interface, the following events occur:
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