參數資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數: 93/119頁
文件大小: 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
65
06/04/02 Revision 1.07
14.1.4
Status Register – Offset 04h (continued)
Bit
Function
Type
Description
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL# decoding
01: medium DEVSEL# decoding
10: slow DEVSEL# decoding
11: reserved
Reset to 01
27
Signaled Target
Abort
R/WC
Set to 1 (by a target device) whenever a target abort cycle
occurs
Reset to 0
28
Received
Target Abort
R/WC
Set to 1 (by a master device) whenever transactions are
terminated with target aborts
Reset to 0
29
Received
Master Abort
R/WC
Set to 1 (by a master) when transactions are terminated with
Master Abort
Reset to 0
30
Signaled
System Error
R/WC
Set to 1 when P_SERR# is asserted
Reset to 0
31
Detected Parity
Error
R/WC
Set to 1 when address or data parity error is detected on the
primary interface
Reset to 0
14.1.5
Revision ID Register – Offset 08h
Bit
Function
Type
Description
7:0
Revision
R/O
Indicates revision number of device. Hardwired to 00h
14.1.6
Class Code Register – Offset 08h
Bit
Function
Type
Description
15:8
Programming
Interface
R/O
Read as 0 to indicate no programming interfaces have been
defined for PCI-to-PCI bridges
23:16
Sub-Class
Code
R/O
Read as 04h to indicate device is PCI-to-PCI bridge
31:24
Base Class
Code
R/O
Read as 06h to indicate device is a bridge device
14.1.7
Cache Line Size Register – Offset 0Ch
Bit
Function
Type
Description
7:0
Cache Line
Size
R/W
Designates the cache line size for the system and is used
when terminating memory write and invalidate transactions
and when prefetching memory read transactions.
Only cache line sizes (in units of 4-byte) which are a power of
two are valid (only one bit can be set in this register; only
00h, 01h, 02h, 04h, 08h, and 10h are valid values).
Reset to 0
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