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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 83/119頁(yè) |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
56
06/04/02 Revision 1.07
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts
one grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one
grant and asserts the next grant, no earlier than one PCI clock cycle later. If the
secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY#
(S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant
during the same PCI clock cycle.
9.2.2
Preemption
Preemption can be programmed to be either on or off, with the default to on (offset
4Ch, bit 31=0). Time-to-preempt can be programmed to 8,16, 32, 64, or 128 (default is
32) clocks.
If the current master occupies the bus and other masters are waiting, the current
master will be preempted by removing its grant (GNT#) after the next master waits for
the time-to-preempt.
9.2.3
Secondary Bus Arbitration Using An External Arbiter
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN#, is tied high. An external arbiter must then be used.
When S_CFN# is tied high, PI7C7300, reconfigures four pins (two per port) to be
external request and grant pins. The S1_GNT#[0] and S2_GNT#[0] pins are
reconfigured to be the external request pins because they are output.
The S1_REQ#[0] and S2_REQ#[0] pins are reconfigured to be the external grant pins
because they are input. When an external arbiter is used, PI7C7300 uses the
S1_GNT#[0] or S2_GNT#[0] pin to request the secondary bus. When the reconfigured
S1_REQ#[0] and S2_REQ#[0] pin is asserted low after PI7C7300 has asserted
S1_GNT#[0] or S2_GNT#[0]. PI7C7300 initiates a transaction on the secondary bus
one cycle later. If grant is asserted and PI7C7300 has not asserted the request,
PI7C7300 parks AD, CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grants outputs, S_GNT#[7:1] and S_GNT#[6:1] are driven
high. The unused secondary bus requests inputs, S1_REQ#[7:1] and S2_REQ#[6:1],
should be pulled high.
9.2.4
Bus Parking
Bus parking refers to driving the AD[31:0], CBE[3:0]#, and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible
for parking the bus or assigning another device to park the bus. A device parks the bus
when the bus is idle, its bus grant is asserted, and the device’s request is not asserted.
The AD and CBE signals should be driven first, with the PAR signal driven one cycle
later.
PI7C7300 parks the primary bus only when P_GNT# is asserted, P_REQ# is de-
asserted, and the primary PCI bus is idle. When P_GNT# is de-asserted, PI7C7300 3-
states the P_AD, P_CBE, and P_PAR signals on the next PCI clock cycle. If PI7C7300
is parking the primary PCI bus and wants to initiate a transaction on that bus, then
PI7C7300 can start the transaction on the next PCI clock cycle by asserting
P_FRAME# if P_GNT# is still asserted.
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相關(guān)代理商/技術(shù)參數(shù) |
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