參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 98/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
viii
06/04/02 Revision 1.07
13
SUPPORTED COMMANDS........................................................................................................59
13.1 PRIMARY INTERFACE ..................................................................................................................59
13.1 PRIMARY INTERFACE (CONTINUED)..............................................................................................60
13.2 SECONDARY INTERFACE .............................................................................................................60
13.2 SECONDARY INTERFACE (CONTINUED).........................................................................................61
14
CONFIGURATION REGISTERS.................................................................................................61
14.1 CONFIGURATION REGISTER 1 AND 2 ...........................................................................................62
14.1.1
Vendor ID Register – Offset 00h.......................................................................................62
14.1.2
Device ID Register – Offset 00h .......................................................................................63
14.1.3
Command Register – Offset 04h ......................................................................................63
14.1.3
Command Register – Offset 04h (continued) ...................................................................64
14.1.4
Status Register – Offset 04h.............................................................................................64
14.1.4
Status Register – Offset 04h (continued)..........................................................................65
14.1.5
Revision ID Register – Offset 08h.....................................................................................65
14.1.6
Class Code Register – Offset 08h ....................................................................................65
14.1.7
Cache Line Size Register – Offset 0Ch ............................................................................65
14.1.8
Primary Latency Timer Register – Offset 0Ch ..................................................................66
14.1.9
Header Type Register – Offset 0Ch..................................................................................66
14.1.10
Primary Bus Number Register – Offset 18h ..................................................................66
14.1.11
Secondary (S1 or S2) Bus Number Register – Offset 18h............................................66
14.1.12
Subordinate (S1 or S2) Bus Number Register – Offset 18h..........................................66
14.1.13
Secondary Latency Timer Register – Offset 18h ..........................................................67
14.1.14
I/O Base Register – Offset 1Ch.....................................................................................67
14.1.15
I/O Limit Register – Offset 1Ch .....................................................................................67
14.1.16
Secondary Status Register – Offset 1Ch ......................................................................67
14.1.16
Secondary Status Register – Offset 1Ch (continued) ...................................................68
14.1.17
Memory Base Register – Offset 20h .............................................................................68
14.1.18
Memory Limit Register – Offset 20h..............................................................................68
14.1.19
Prefetchable Memory Base Register – Offset 24h ........................................................69
14.1.20
Prefetchable Memory Limit Register – Offset 24h.........................................................69
14.1.21
Prefetchable Memory Base Address Upper 32-bits Register – Offset 28h ...................69
14.1.22
Prefetchable Memory Limit Address Upper 32-bits Register – Offset 2Ch ..................69
14.1.23
I/O Base Address Upper 16-bits Register – Offset 30h.................................................70
14.1.24
I/O Limit Address Upper 16-bits Register – Offset 30h .................................................70
14.1.25
ECP Pointer Register – Offset 34h................................................................................70
14.1.26
Bridge Control Register – Offset 3Ch............................................................................70
14.1.26
Bridge Control Register – Offset 3Ch (continued).........................................................71
14.1.26
Bridge Control Register – Offset 3Ch (continued).........................................................72
14.1.27
Diagnostic / Chip Control Register – Offset 40h............................................................72
14.1.27
Diagnostic / Chip Control Register – Offset 40h (continued).........................................73
14.1.28
Arbiter Control Register – Offset 40h ............................................................................73
14.1.29
Upstream Memory Control Register – Offset 48h .........................................................74
14.1.30
Hot Swap Switch Time Slot Register – Offset 4Ch .......................................................74
14.1.31
Upstream (S1 or S2 to P) Memory Base Register – Offset 50h....................................74
14.1.32
Upstream (S1 or S2 to P) Memory Limit Register – Offset 50h ....................................75
14.1.33
Upstream (S1 or S2 to P) Memory Base Upper 32 bits Register – Offset 54h .............75
14.1.34
Upstream (S1 or S2 to P) Memory Limit Upper 32 bits Register – Offset 58h ..............75
14.1.35
P_SERR# Event Disable Register – Offset 64h............................................................75
14.1.35
P_SERR# Event Disable Register – Offset 64h (continued).........................................76
14.1.36
Secondary Clock Control Register – Offset 68h............................................................76
14.1.36
Secondary Clock Control Register – Offset 68h (continued).........................................77
14.1.37
Port Option Register – Offset 74h .................................................................................77
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