參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 112/119頁(yè)
文件大?。?/td> 880K
代理商： PI7C7300NA
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
82
06/04/02 Revision 1.07
14.1.55
Hot Swap Control and Status Register – Offset C0h
Bit
Function
Type
Description
16
Not Available
R/O
Not used. Returns 0 when read. Reset to 0
17
ENUM Signal
Mask
R/W
0: Mask ENUM# signal
1: Enable ENUM# signal
18
Not Available
R/O
Not used. Returns 0 when read. Reset to 0
19
LED ON/OFF
R/W
LOO signal (LED on/off)
0: LED on
1: LED off
Reset to 0
21:20
Not Available
R/O
Not Used. Returns 0 when read. Reset to 0
22
ENUM# Status
– Extraction
R/W
0: ENUM# asserted
1: ENUM# not asserted
Reset to 0
23
ENUM# Status
– Insertion
R/W
0: ENUM# asserted
1: ENUM# not asserted
Reset to 0
31:24
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
15
Bridge Behavior
A PCI cycle is initiated by asserting the FRAME# signal. In a bridge, there are a
number of possibilities. Those possibilities are summarized in the table below:
15.1
Bridge Actions for Various Cycle Types
Initiator
Target
Response
Master on Primary
Target on Primary
PI7C7300 does not respond. It
detects this situation by decoding the
address as well as monitoring the
P_DEVSEL# for other fast and
medium devices on the Primary Port.
Master on Primary
Target on Secondary
PI7C7300 asserts P_DEVSEL#,
terminates the cycle normally if it is
able to be posted, otherwise return
with a retry. It then passes the cycle
to the appropriate port. When the
cycle is complete on the target port, it
will wait for the initiator to repeat the
same cycle and end with normal
termination.
Master on Primary
Target not on Primary nor
Secondary Port
PI7C7300 does not respond and the
cycle will terminate as master abort.
Master on Secondary
Target on the same
Secondary Port
PI7C7300 does not respond.
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