參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 67/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
41
06/04/02 Revision 1.07
§
If the parity error response bit is set in the command register, PI7C7300 does not
claim the transaction with P_DEVSEL#; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C7300 proceeds
normally and accepts the transaction if it is directed to or across PI7C7300.
§
PI7C7300 sets the detected parity error bit in the status register.
§
PI7C7300 asserts P_SERR# and sets signaled system error bit in the status
register, if both the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the command register.
When PI7C7300 detects an address parity error on the secondary interface, the
following events occur:
§
If the parity error response bit is set in the bridge control register, PI7C7300 does
not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the
transaction to terminate in a master abort. If parity error response bit is not set,
PI7C7300 proceeds normally and accepts transaction if it is directed to or across
PI7C7300.
§
PI7C7300 sets the detected parity error bit in the secondary status register.
§
PI7C7300 asserts P_SERR# and sets signaled system error bit in status register,
if both of the following conditions are met:
-
The SERR# enable bit is set in the command register.
-
The parity error response bit is set in the bridge control register.
7.2
Data Parity Errors
When forwarding transactions, PI7C7300 attempts to pass the data parity condition
from one interface to the other unchanged, whenever possible, to allow the master and
target devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events
that occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C7300.
7.2.1
Configuration Write Transactions to Configuration Space
When PI7C7300 detects a data parity error during a Type 0 configuration write
transaction to PI7C7300 configuration space, the following events occur:
§
If the parity error response bit is set in the command register, PI7C7300 asserts
P_TRDY# and writes the data to the configuration register. PI7C7300 also asserts
P_PERR#. If the parity error response bit is not set, PI7C7300 does not assert
P_PERR#.
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