參數資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數： 76/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
vi
06/04/02 Revision 1.07
TABLE OF CONTENTS
1
INTRODUCTION...............................................................................................................................1
2
BLOCK DIAGRAM............................................................................................................................2
3
SIGNAL DEFINITIONS .....................................................................................................................3
3.1
SIGNAL TYPES .............................................................................................................................3
3.2
PRIMARY BUS INTERFACE SIGNALS ...............................................................................................3
3.2
PRIMARY BUS INTERFACE SIGNALS (CONTINUED)...........................................................................4
3.2
PRIMARY BUS INTERFACE SIGNALS (CONTINUED)...........................................................................5
3.3
SECONDARY BUS INTERFACE SIGNALS..........................................................................................5
3.3
SECONDARY BUS INTERFACE SIGNALS (CONTINUED) .....................................................................6
3.3
SECONDARY BUS INTERFACE SIGNALS (CONTINUED) .....................................................................7
3.4
CLOCK SIGNALS ...........................................................................................................................7
3.5
MISCELLANEOUS SIGNALS ............................................................................................................8
3.6
HOT-SWAP SIGNALS ....................................................................................................................8
3.7
JTAG BOUNDARY SCAN SIGNALS .................................................................................................8
3.8
POWER AND GROUND...................................................................................................................9
3.9
PI7C7300 PBGA PIN LIST...........................................................................................................9
3.9
PI7C7300 PBGA PIN LIST (CONTINUED) ....................................................................................10
3.9
PI7C7300 PBGA PIN LIST (CONTINUED) ....................................................................................11
4
PCI BUS OPERATION....................................................................................................................11
4.1
TYPES OF TRANSACTIONS ..........................................................................................................12
4.2
SINGLE ADDRESS PHASE............................................................................................................12
4.3
DUAL ADDRESS PHASE...............................................................................................................13
4.4
DEVICE SELECT (DEVSEL#) GENERATION .................................................................................13
4.5
DATA PHASE ..............................................................................................................................13
4.6
WRITE TRANSACTIONS ...............................................................................................................13
4.6.1
Memory Write Transactions ..............................................................................................14
4.6.2
Memory Write and Invalidate Transactions.......................................................................15
4.6.3
Delayed Write Transactions..............................................................................................15
4.6.4
Write Transaction Address Boundaries ............................................................................16
4.6.5
Buffering Multiple Write Transactions ...............................................................................16
4.6.6
Fast Back-to-Back Write Transactions .............................................................................17
4.7
READ TRANSACTIONS.................................................................................................................17
4.7.1
Prefetchable Read Transactions.......................................................................................17
4.7.2
Non-Prefetchable Read Transactions...............................................................................17
4.7.3
Read Prefetch Address Boundaries..................................................................................18
4.7.4
Delayed Read Requests ...................................................................................................19
4.7.5
Delayed Read Completion With Target ............................................................................19
4.7.6
Delayed Read Completion on Initiator Bus .......................................................................20
4.8
CONFIGURATION TRANSACTIONS ................................................................................................21
4.8.1
Type 0 Access to PI7C7300 .............................................................................................21
4.8.2
Type 1 to Type 0 Conversion............................................................................................22
4.8.3
Type 1 to Type 1 Forwarding ............................................................................................23
4.8.4
Special Cycles...................................................................................................................24
4.9
TRANSACTION TERMINATION.......................................................................................................25
4.9.1
Master Termination Initiated by PI7C7300........................................................................26
4.9.2
Master Abort Received by PI7C7300................................................................................26
4.9.3
Target Termination Received by PI7C7300......................................................................27
4.9.4
Target Termination Initiated by PI7C7300 ........................................................................29
4.10 CONCURRENT MODE OPERATION................................................................................................31
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