參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 70/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
44
06/04/02 Revision 1.07
§
PI7C7300 captures the parity error condition to forward it back to the initiator on
the secondary bus.
A delayed write transaction is completed on the initiator bus when the initiator repeats
the write transaction with the same address, command, data, and byte enable bits as
the delayed write command that is at the head of the posted data queue. Note that the
parity bit is not compared when determining whether the transaction matches those in
the delayed transaction queues.
Two cases must be considered:
§
When parity error is detected on the initiator bus on a subsequent re-attempt of the
transaction and was not detected on the target bus
§
When parity error is forwarded back from the target bus
For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C7300 has write status to return, the following events occur:
§
PI7C7300 first asserts P_TRDY# and then asserts P_PERR# two cycles later, if
the primary interface parity-error-response bit is set in the command register.
§
PI7C7300 sets the primary interface parity-error-detected bit in the status register.
§
Because there was not an exact data and parity match, the write status is not
returned and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300 has write status to return, the following events occur:
§
PI7C7300 first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
§
PI7C7300 sets the secondary interface parity-error-detected bit in the secondary
status register.
§
Because there was not an exact data and parity match, the write status is not
returned and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the
target bus and the parity error condition was not originally detected on the initiator bus,
the following events occur:
§
PI7C7300 asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity-error-response bit is set in the command register of the primary
interface.
-
The parity-error-response bit is set in the bridge control register of the
secondary interface.
§
PI7C7300 completes the transaction normally.
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