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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 74/119頁 |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
48
06/04/02 Revision 1.07
TABLE 7-3. SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT
Primary
Data
Parity Bit
Transaction
Type
Direction
Bus Where
Error Was
Detected
Primary /
Secondary
Parity Error
Response Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
1 / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
1
Posted Write
Upstream
Primary
1 / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
0
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
1 / x
0
Delayed Write
Upstream
Secondary
x / x
X = don’t care
Table 7–4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
§
The PI7C7300 must be a master on the secondary bus.
§
The parity error response bit must be set in the bridge control register of
secondary interface.
§
The S_PERR# signal is detected asserted or a parity error is detected on the
secondary bus.
TABLE 7-4. SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT
Secondary
Detected Parity
Detected Bit
Transaction
Type
Direction
Bus Where
Error Was
Detected
Primary /
Secondary
Parity Error
Response Bits
0
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / 1
0
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
0
Posted Write
Downstream
Primary
x / x
1
Posted Write
Downstream
Secondary
x / 1
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
0
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / 1
0
Delayed Write
Upstream
Primary
x / x
0
Delayed Write
Upstream
Secondary
x / x
X= don’t care
Table 7–5 shows assertion of P_PERR#. This signal is set under the following
conditions:
§
PI7C7300 is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
§
The parity-error-response bit must be set in the command register of primary
interface.
§
PI7C7300 detects a data parity error on the primary bus or detects S_PERR#
asserted during the completion phase of a downstream delayed write transaction
on the target (secondary) bus.
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