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參數資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數： | 63/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
38
06/04/02 Revision 1.07
PI7C7300 does not combine or merge write transactions:
§
PI7C7300 does not combine separate write transactions into a single write
transaction—this optimization is best implemented in the originating master.
§
PI7C7300 does not merge bytes on separate masked write transactions to the
same DWORD address—this optimization is also best implemented in the
originating master.
§
PI7C7300 does not collapse sequential write transactions to the same address into
a single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
6.2
General Ordering Guidelines
Independent transactions on primary and secondary buses have a relationship only
when those transactions cross PI7C7300.
The following general ordering guidelines govern transactions crossing PI7C7300:
§
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with
a termination other than target retry.
§
Requests terminated with target retry can be accepted and completed in any order
with respect to other transactions that have been terminated with target retry. If the
order of completion of delayed requests is important, the initiator should not start a
second delayed transaction until the first one has been completed. If more than
one delayed transaction is initiated, the initiator should repeat all delayed
transaction requests, using some fairness algorithm. Repeating a delayed
transaction cannot be contingent on completion of another delayed transaction.
Otherwise, a deadlock can occur.
§
Write transactions flowing in one direction have no ordering requirements with
respect to write transactions flowing in the other direction. PI7C7300 can accept
posted write transactions on both interfaces at the same time, as well as initiate
posted write transactions on both interfaces at the same time.
§
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master.
This is true for PI7C7300 and must also be true for other bus agents. Otherwise, a
deadlock can occur.
§
PI7C7300 accepts posted write transactions, regardless of the state of completion
of any delayed transactions being forwarded across PI7C7300.
6.3
Ordering Rules
Table 6–1 shows the ordering relationships of all the transactions and refers by
number to the ordering rules that follow.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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