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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 96/119頁 |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
68
06/04/02 Revision 1.07
14.1.16
Secondary Status Register – Offset 1Ch (continued)
Bit
Function
Type
Description
26:25
DEVSEL#
timing
R/O
DEVSEL# timing (medium decoding)
00: fast DEVSEL# decoding
01: medium DEVSEL# decoding
10: slow DEVSEL# decoding
11: reserved
Reset to 01
27
Signaled Target
Abort
R/WC
Set to 1 (by a target device) whenever a target abort cycle
occurs on its secondary (S1 or S2) interface
Reset to 0
28
Received
Target Abort
R/WC
Set to 1 (by a master device) whenever transactions on its
secondary (S1 or S2) interface are terminated with target
abort
Reset to 0
29
Received
Master Abort
R/WC
Set to 1 (by a master) when transactions on its secondary
(S1 or S2) interface are terminated with Master Abort
Reset to 0
30
Received
System Error
R/WC
Set to 1 when S1_SERR# or S2_SERR# is asserted
Reset to 0
31
Detected Parity
Error
R/WC
Set to 1 when address or data parity error is detected on the
secondary (S1 or S2) interface
Reset to 0
14.1.17
Memory Base Register – Offset 20h
Bit
Function
Type
Description
3:0
R/O
Lower four bits of register are read only and return 0.
Reset to 0
15:4
Memory Base
Address [15:4]
R/W
Defines the bottom address of an address range for the
bridge to determine when to forward memory transactions
from one interface to the other. The upper 12 bits correspond
to address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be 0.
Reset to 0
14.1.18
Memory Limit Register – Offset 20h
Bit
Function
Type
Description
19:16
R/O
Lower four bits of register are read only and return 0.
Reset to 0
31:20
Memory Limit
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory transactions from one
interface to the other. The upper 12 bits correspond to
address bits [31:20] and are writable. The lower 20 bits
corresponding to address bits [19:0] are assumed to be
FFFFFh.
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