參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 26/119頁(yè)
文件大小： 880K
代理商： PI7C7300NA
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
4
06/04/02 Revision 1.07
3.2
Primary Bus Interface Signals (continued)
Name
Pin #
Type
Description
P_IRDY#
V13
PSTS
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before
tri-stated, it is driven to a de-asserted state for
one cycle.
P_TRDY#
U13
PSTS
Primary TRDY (Active LOW). Driven by the
target of a transaction to indicate its ability to
complete current data phase on the primary side.
Once asserted in a data phase, it is not de-
asserted until the end of the data phase. Before
tri-stated,
it is driven to a de-asserted state for one cycle.
P_DEVSEL#
Y14
PSTS
Primary Device Select (Active LOW). Asserted
by the target indicating that the device is
accepting the transaction. As a master,
PI7C7300 waits for the assertion of this signal
within 5 cycles of P_FRAME# assertion;
otherwise, terminate with master abort. Before tri-
stated, it is driven to a
de-asserted state for one cycle.
P_STOP#
W14
PSTS
Primary STOP (Active LOW). Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
P_LOCK#
V14
PSTS
Primary LOCK (Active LOW). Asserted by the
master for multiple transactions to complete.
P_IDSEL
Y10
PI
Primary ID Select. Used as a chip select line for
Type 0 configuration access to PI7C7300
configuration space.
P_PERR#
Y15
PSTS
Primary Parity Error (Active LOW). Asserted
when a data parity error is detected for data
received on the primary interface. Before being
tri-stated, it is driven to a de-asserted state for
one cycle.
P_SERR#
W15
POD
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system
error condition. PI7C7300 drives this pin on:
§
Address parity error
§
Posted write data parity error on target bus
§
Secondary S1_SERR# or S2_SERR#
asserted
§
Master abort during posted write transaction
§
Target abort during posted write transaction
§
Posted write transaction discarded
§
Delayed write request discarded
§
Delayed read request discarded
§
Delayed transaction master timeout
This signal requires an external pull-up resistor for
proper operation.
P_REQ#
W6
PTS
Primary Request (Active LOW). This is asserted
by PI7C7300 to indicate that it wants to start a
transaction on the primary bus.
PI7C7300 de-
asserts this pin for at least 2 PCI clock cycles
before asserting it again.
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